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Masataka Ohta
Masataka Ohta
Toshiba
Logic gate
CMOS
NMOS logic
Integrated circuit layout
Silicon-germanium
1
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23
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Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique
2009
IEEE Transactions on Electron Devices
E. Morifuji
Hirotoshi Aikawa
H. Yoshimura
Akihiro Sakata
Masataka Ohta
Makoto Iwai
Fumitomo Matsuoka
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