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U. Gruening

6

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A 0.135 pm2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/l6Gb DRAM

2000
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Gate prespacers for high density DRAMs

1999 VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
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A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

1998 VLSIT | Symposium on VLSI Technology
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A 0.21 j" 7F2 Trench Cell With a Locally-Open Glo ally-Folded Dual Bitline For 1Gb/4Gb DRAM

1998
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Promise of silicon wafer microguides for future neutron optical elements

1992
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Citations (3)