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Jacob Savir

New Jersey Institute of Technology
IBM

101

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3196

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ECE 251 - Digital Design

2018
- Jacob Savir
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ECE 354 - Digital Test

2018
- Jacob Savir
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Effect of BIST Pretest on IC Defect Level(Dependable Computing)

2006 IEICE Transactions on Information and Systems
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Effect of BIST Pretest on IC Defect Level

2006 IEICE Transactions on Information and Systems
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Built-in online and offline test of airborne digital systems

2005 IEEE Transactions on Instrumentation and Measurement
- Jacob Savir
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Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)

2005 IEICE Transactions on Information and Systems
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Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths

2005 IEICE Transactions on Information and Systems
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Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)

2005 IEICE Transactions on Information and Systems
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Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)

2005 IEICE Transactions on Information and Systems
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Scan Latch Design for Test Applications

2004 Journal of Electronic Testing
- Amit M. Sheth
- Jacob Savir
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