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Vita Pi-Ho Hu

National Chiao Tung University
National Central University

98

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643

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Study on the efficient erase opeartion in ferroelectric HfO2 FeFET toward 3D vertical structure

2021
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Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials based FETs at 2nm Node

2021 ISCAS | International Symposium on Circuits and Systems
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Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors

2021 ECS Journal of Solid State Science and Technology
- Manish Gupta
- Vita Pi-Ho Hu
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Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS₂ FETs for SoC Scaling

2020 IEEE Transactions on Electron Devices
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Negative Capacitance Junctionless Device with Mid-gap Work Function for Low Power Applications

2020 IEEE Electron Device Letters
- Manish Gupta
- Vita Pi-Ho Hu
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Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)

2020 IEEE Transactions on Electron Devices
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Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design

2020 ISCAS | International Symposium on Circuits and Systems
- Yen-Wei Lee
- Vita Pi-Ho Hu
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Subthreshold Behavior of Ferroelectric Junctionless Transistor

2020 VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
- Manish Gupta
- Vita Pi-Ho Hu
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Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET

2019 ISQED | International Symposium on Quality Electronic Design
- Hung-Han Lin
- Vita Pi-Ho Hu
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Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs

2019 IEEE Journal of the Electron Devices Society
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