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Quan Nguyen
Quan Nguyen
IBM
Reduced instruction set computing
Computer science
CMOS
Microprocessor
Instructions per cycle
2
Papers
11
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A 200 MHz 2.5 V 4 W superscalar RISC microprocessor
1996
ISSCC | International Solid-State Circuits Conference
Hector Sanchez
Lee Evan Eisen
C Croxton
A. Piejko
Carmine Nicoletta
I. Vo
B. Branson
Wen Wang
Quan Nguyen
T. Buti
Louis L. Hsu
M. J. Saccamango
S. Ratanaphanyara
Ross Philip
Jose Alvarez
S. Weitzel
G. Gerosa
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A 1.2 W 66 MHz superscalar RISC microprocessor for set-tops, video games, and PDAs
1995
ISSCC | International Solid-State Circuits Conference
D. Pham
James Allan Kahle
Deene Ogden
Michael Putrino
Tai Ngo
K. Hoover
Cang Tran
Mark R. Sweet
Hung Hua
Quan Nguyen
Soummya Mallick
Lee Evan Eisen
Albert J. Loper
R. Chitturi
T. Lyon
B. Ho
Rajesh Bhikhubhai Patel
E. Cheesebrough
Belliappa Manavattira Kuttanna
A. Piejko
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Citations (4)
1