Old Web
English
Sign In
Acemap
>
authorDetail
>
Chih-Chang Lin
Chih-Chang Lin
TSMC
Electronic engineering
Computer science
Transceiver
Electrical engineering
Wireline
3
Papers
28
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (2)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET
2019
VLSIC | Symposium on VLSI Circuits
Dirk Pfaff
Shahaboddin Moazzeni
Leisheng Gao
Mei-Chen Chuang
Xin-Jie Wang
Chai Palusa
Robert Abbott
Rolando Ramirez
Maher Amer
Ming-Chieh Huang
Chih-Chang Lin
Fred Kuo
Wei-Li Chen
Tae Young Goh
Kenny Hsieh
Show All
Source
Cite
Save
Citations (4)
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET
2019
CICC | Custom Integrated Circuits Conference
Dirk Pfaff
Robert Abbott
Xin-Jie Wang
Babak Zamanlooy
Shahaboddin Moazzeni
Raleigh Smith
Chih-Chang Lin
Show All
Source
Cite
Save
Citations (3)
1