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Yongseok Ahn

Samsung

6

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51

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Optimized cell structure for FinFET array Flash memory

2004 ESSCIRC | European Solid-State Circuits Conference
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Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond

2004 VLSIT | Symposium on VLSI Technology
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Robust memory cell capacitor using multi-stack storage node for high performance in 90 nm technology and beyond

2003 VLSIT | Symposium on VLSI Technology
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The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon

2002 Microelectronics Reliability
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A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 /spl mu/m technology node and beyond

2000 IEEE Transactions on Electron Devices
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