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Y.-M. Niquet
Y.-M. Niquet
STMicroelectronics
Engineering
Electronic engineering
Nanowire
Strain (chemistry)
Semiconductor device modeling
2
Papers
19
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Impact of strain on access resistance in planar and nanowire CMOS devices
2017
VLSIT | Symposium on VLSI Technology
R. Berthelon
F. Andneu
François Triozon
M. Casse
L. Bourdet
G. Ghibaudo
D. Rideau
Y.-M. Niquet
S. Barraud
P. Nguyen
C. Le Royer
J. Lacord
C. Tabone
O. Rozeau
Didier Dutartre
A. Claverie
E. Josse
F. Arnaud
M. Vinet
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Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects
2013
VLSIT | Symposium on VLSI Technology
S. Barraud
R. Coquand
V. Maffini-Alvaro
M.-P. Samson
J.-M. Hartmann
L. Tosti
M. Casse
Viet Hung Nguyen
François Triozon
Y.-M. Niquet
C. Tabone
P. Perreau
F. Allain
C. Vizioz
C. Comboroure
F. Aussenac
S. Monfray
G. Ghibaudo
F. Bœuf
B. De Salvo
O. Faynot
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Citations (19)
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