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V. Vasireddy
V. Vasireddy
Tennessee Technological University
Optoelectronics
Logic gate
CMOS
Calibration
MOSFET
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Simulation and Experimental Results of a 0.15µm Independent Double Gated CMOS Transistor
2010
BUGIMNS | Biennial University/Government/Industry Micro/Nano Symposium
V. Vasireddy
Stephen A. Parke
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