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George Gristede

IBM

20

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173

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SynTunSys: A Synthesis Parameter Autotuning System for Optimizing High-Performance Processors

2019
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A Scalable Multi-TeraOPS Core for AI Training and Inference

2019
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A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs.

2016
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Power reduction by aggressive synthesis design space exploration

2013 ISLPED | International Symposium on Low Power Electronics and Design
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A new methodology for power-aware transistor sizing: free power recovery (FPR)

2009 PATMOS | Power and Timing Modeling, Optimization and Simulation
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The opportunity cost of low power design: a case study in circuit tuning

2009 ISLPED | International Symposium on Low Power Electronics and Design
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Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies

2005 GLSVLSI | Great Lakes Symposium on VLSI
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Characterization of logic circuit techniques for high leakage CMOS technologies

2004 GLSVLSI | Great Lakes Symposium on VLSI
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Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design

2001 ISLPED | International Symposium on Low Power Electronics and Design
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A comparison of dual-rail pass transistor logic families in 1.5V, 0.18μm CMOS technology for low power applications

2000 GLSVLSI | Great Lakes Symposium on VLSI
- George Gristede
- Wei Hwang
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