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Giovanni Cesura

STMicroelectronics

5

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Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

2006 IEEE Circuits and Systems Magazine
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A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals

2006 ESSCIRC | European Solid-State Circuits Conference
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An 80MHz 4/spl times/ oversampled cascaded /spl Delta//spl Sigma/-pipelined ADC with 75dB DR and 87dB SFDR

2005 ISSCC | International Solid-State Circuits Conference
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Mixed Mode Sigma-Delta ADC Design for High Quality Audio

2000
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