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Don Plass
Don Plass
IBM
Computer science
Electronic engineering
Architecture
Dram
System on a chip
3
Papers
64
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Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
2012
VLSIC | Symposium on VLSI Circuits
John E. Barth
Don Plass
Adis Vehabovic
Rajiv V. Joshi
Rouwaida Kanj
Steven Burns
Todd Weaver
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A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
2011
IEEE Journal of Solid-state Circuits
John E. Barth
Don Plass
Erik A. Nelson
Charlie Hwang
Gregory J. Fredeman
Michael A. Sperling
Abraham Mathews
Toshiaki Kirihata
William Robert Reohr
Kavita Nair
Nianzheng Caon
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Citations (47)
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache
2010
ISSCC | International Solid-State Circuits Conference
John E. Barth
Don Plass
Erik A. Nelson
Charlie Hwang
Gregory J. Fredeman
Michael A. Sperling
Abraham Mathews
William Robert Reohr
Kavita Nair
Nianzheng Cao
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Citations (17)
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