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Geng-Cing Lin

National Chiao Tung University

6

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17

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A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

2012 ISLPED | International Symposium on Low Power Electronics and Design
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High-performance 0.6V V MIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

2012 ISCAS | International Symposium on Circuits and Systems
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Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

2012 APCCAS | Asia Pacific Conference on Circuits and Systems
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An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

2012 ISCAS | International Symposium on Circuits and Systems
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An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

2012 VLSI-DAT | International Symposium on VLSI Design, Automation and Test
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