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Yung-Hsiang Ho

National Taiwan University of Science and Technology

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Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

2015 IEEE Transactions on Very Large Scale Integration Systems
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A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism

2013 VLSI-DAT | International Symposium on VLSI Design, Automation and Test
- Chia-Yu Yao
- Yung-Hsiang Ho
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