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Hiroshi Komurasaki

Mitsubishi Electric

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Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

2001 IEEE Transactions on Electron Devices
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Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

2000 VLSIT | Symposium on VLSI Technology
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Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

2000
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