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    Small Signal Synchronous Stability Analysis of Grid-Connected VSC in Weak Grid
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    SIGNAL (programming language)
    Oscillation (cell signaling)
    Small-signal model
    The amplitude, frequency and phase angle of the grid voltage are essential three components to ensure synchronization for grid interactive inverters. Synchronous reference frame-phase locked loop (SRF-PLL) is widely used to obtain these components. Although the SRF-PLL shows a perfect performance under ideal grid conditions, its performance deteriorates under unbalanced and distorted grid conditions. Therefore, researchers have been working to provide more advanced PLL methods. A dual third order generalized integrator PLL (DTOGI-PLL) and quasi-type-1 PLL (QT1-PLL) are two PLL methods that have come to the fore in grid synchronization recently. As with any method, these PLL methods have both advantages and disadvantages. The aim of this study is to integrate the advantages of the two methods, and to develop a new PLL method with better performance than these two methods. It means that the proposed PLL has the adaptive filtering capability of the DTOGI-PLL and fast transient response of the QT1-PLL. The effectiveness of the proposed PLL is confirmed by experimental results. The experimental results demonstrate that the proposed PLL is a more effective method than the DTOGI-PLL and QT1-PLL under adverse grid conditions.
    PLL multibit
    Abstract In this paper, an integral‐type half‐tangent phase‐locked loop (IHTan‐PLL) is proposed for the varying‐frequency AC grids of more electric aircraft (MEA). First, the performance of the synchronous reference frame phase‐locked loop (SRF‐PLL) and half‐tangent phase‐locked loop (HTan‐PLL) is discussed from a large‐signal viewpoint. When the frequency changes largely, the SRF‐PLL has many oscillations and endures a rather long transient process. The HTan‐PLL can address the large frequency jumps. However, for the varying‐frequency AC grids with harmonic disturbances, the HTan‐PLL still has oscillations in estimating the frequency when the frequency jumps largely. To enhance the performance of the SRF‐PLL and HTan‐PLL, the IHTan‐PLL is developed for the varying‐frequency AC grids with harmonic disturbances. The IHTan‐PLL performs better than the SRF‐PLL and HTan‐PLL in addressing the large frequency jumps. Specifically, under any large frequency changes, the IHTan‐PLL still converges to the equilibrium point (0,0), and no oscillations emerge. In addition, the IHTan‐PLL has better steady‐state accuracy in estimating the frequency than the SRF‐PLL and HTan‐PLL. The experimental results also demonstrate the superior performance of the proposed IHTan‐PLL.
    PLL multibit
    Harmonic
    Citations (0)
    Electromechanical oscillations are composed of local oscillation and inter-area oscillation. With the development of electric power systems, inter-area oscillation has been a major concern. Inter-area oscillation, which aroused by many generators in different areas, will not be damped effectively if only a few generators install power system stabilizer which could be very effectively to damp local oscillation, while flexible ac transmission system(FACTS) may have a good effect because of its installing flexibly and good dynamic performance. So FACTS is used to damping inter-area oscillation in this paper. With the developing of power electric, FACTS have a good progress, and are used widely in power system. In this paper, four kinds of FACTS are introduced while their models are based in power system analysis software package(PSASP). The power in area oscillation is constant in non-damping power system, which is testified in this paper. So a damping controller of FACTS is designed with the theory of deducing the power in area oscillation. In this paper, SVC is taken for example to design the damping controller, and proved the effect by simulation in PSASP. Damping controllers of other kinds of FACTS including TCSC, STATCOM and SSSC are also designed, which also have good effect to damping inter-area oscillation by simulation. The power oscillation between two areas is damped quickly while these FACTS are installed. The results indicated that it is effective to damp the inter-area oscillation through FACTS.
    Oscillation (cell signaling)
    Low-frequency oscillation
    Stabilizer (aeronautics)
    Damping torque
    Self-oscillation
    Citations (4)
    The orthogonal-signal-generator-based phase-locked loops (OSG-PLLs) are among the most popular single-phase PLLs within the areas of power electronics and power systems, mainly because they are often easy to be implemented and offer a robust performance against the grid disturbances. The main aim of this paper is to present a survey of the comparative performance evaluation among the state-of-the-art OSG-PLLs (include Delay-PLL, Deri-PLL, Park-PLL, SOGI-PLL, DOEC-PLL, VTD-PLL, CCF-PLL, and TPFA-PLL) under different grid disturbances such as voltage sags, phase, and frequency jumps, and in the presence of dc offset, harmonic components, and white noise in their input. This analysis provides a useful insight about the advantages and disadvantages of these PLLs. The performance enhancement of Delay-PLL, Deri-PLL, and CCF-PLL by including a moving average filter into their structure is another goal of this paper.
    SIGNAL (programming language)
    Citations (333)
    This chapter contains sections titled: PLL Basic PLL Design Stability of the PLL Tracking Working Ranges of PLL Digital PLL PLL Phase Noise PLL Time Jitter Spurious Signals Synchronized Oscillators
    PLL multibit
    Spurious relationship
    Citations (0)
    Phase locked loop (PLL) being a mixed signal circuit involves design challenges at high frequencies. In this work a mixed signal PLL for faster phase and frequency locking is designed. The PLL is designed and synthesized using GPDK090 library of CMOS 90 nm process in CADENCE Virtuoso Analog Design Environment for an operating frequency of 1 GHz. Its locking time is 280.6 ns and observed to consume a power of 11.9 mW with a 1.8 V supply voltage. The complete layout of the PLL is drawn in CADENCE Virtuoso XL and its behaviour and performance is observed in Spectre.
    Cadence
    PLL multibit
    SIGNAL (programming language)
    The modern power system where the numbers of Distributed Energy Resources (DERs) are connected to the grid, forces to proliferation in power electronics devices, in this scenario proper and fast synchronization become very important. To achieve this many synchronization techniques have been discussed in literatures. For this purposes PLL is widely used because of its simple implementation and robust structure. The Generalized Integrator (GI) based Phase-Locked Loop (PLL) has become favorite among researchers specially Second-Order-GI-PLL. It is widely used in grid connected single-phase system because of its advantages over conventional and others PLL. However, in weak grid conditions the performance of the SOGI-PLL greatly affected, it is sensitive to DC-offset and sub-harmonics. It is having frequency feedback loop that degrade the performance of the PLL during rapid changes in the frequency. To overcome these issues a Derivative Element (DE) based PLL is used. DE-PLL having no frequency feedback loop that allows it to achieve high performance even during sudden frequency variation. In this literature both the SOGI-PLL and DE-PLL have discussed in detailed and their performance is analyzed under weak grid condition by using MATLAB/SIMULINK.
    PLL multibit