Experimental and numerical study on thin silicon wafer CO2 laser cutting and damage investigation
Kaveh MoghadasiKhairul Fikri TamrinNadeem Ahmed SheikhAbdul Rahman KramPierre BarroyFahizan MahmudAmir Azam Khan
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Laser cutting
Usually when cutting thicker material we need higher power laser during laser cutting. If we use a saw to cut the situation will be different. In this paper we report a novel technology for thick glass cutting with a small power laser saw. The laser saw is made of 532nm green laser with long pulse width 550µs. It is not a special but an ordinary green laser. The special focus point of laser can be moving up and down at high frequency with the control lens. During cutting it works like a saw so we call it laser saw. The average power of the laser is approximately 0.7W much less than 1W. However with this small power laser we can cut over 10mm thick glass. The cutting speed can be 1m/min. The roughness of the cutting surface is about 10 micron meters. There is no obvious crack on the edge of kerf. It shows great potential application with this laser saw technology.
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It may be more cost‐effective to produce larger diameter silicon CZ solar cells. However, greater thickness is anticipated to be necessary for larger diameter wafers to withstand wafering, cell processing, and handling. No means of quantifying this anticipated thickness increase is available to provide standards or guide for cell manufacturers. In this paper equations relating wafer thickness and diameter were derived by using fracture mechanics analysis. An analytical model was used as a guideline to estimate minimum silicon wafer thickness vs. diameter requirements for ID wafering in terms of fracture mechanics parameters. The model also indicated the minimum wafer side support required for various wafer thickness at any diameter.
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In the heat treatment of silicon wafer, temperature control of the wafer surface is very important. This paper investigates the rapid radiative heating characteristics of the silicon wafers arranged in a row in the vertical heating furnace by the experiment and the numerical simulation. In present test, a wafer pitch was changed from 54 mm to 216 mm. The results showed that the maximum difference of surface temperature decreased with increase of a pitch of the silicon wafer. The maximum temperature difference was about 5℃, when a wafer pitch was 108mm and ramp-up ratio was 150℃/min. Simulation and experimental result agreed very well.
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A new polishing machine has been constructed for the fabrication of bonded-wafer silicon-on-insulator (bonded-wafer SOI) through a numerically controlled polishing technique. The polishing machine is equipped with 32 small-area tools which produce the variation of polishing pressure over a wafer surface. The tools do not rotate. Instead, the wafers being polished perform an oscillatory motion. A tool removal profile which was adequate for selectively polishing one place on a wafer without affecting its neighboring areas was obtained. As a result of its test operation, the initial thickness deviation of σ=380 nm of the top Si layer of a bonded-wafer SOI sample has been improved to σ=48 nm.
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In the silicon wafer polishing process, the mounting of wafer on the polishing head could be greatly influential in final quality of finished wafers. This paper focuses on the waxless wafer mounting technique which could replace the traditional wax wafer mounting. Mounting of wafers on the carrier block using a wetted porous template provides a simple way of securing wafer on polishing head for precision wafer polishing. Demounting of wafers from the porous pad is carried out by using the water jet impingement which takes only a couple of seconds for wafer demounting. A series of wafer polishing tests of 8 inch silicon wafers using the present wafer mounting system found that the developed waxless wafer mounting could be quite suitable for producing the wafers of the excellent surface qualities by meeting industry standard such as SBIR, LLS, and production yield.
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As device pattern size is shrinking to below 65nm on wafer, the small amount of CD variation on wafer field determine the wafer yield. Most of the wafer field CD variations come from mask CD variations across mask field. By correction of dose and transmittance on mask using wafer field CD variation, wafer CD uniformity can be extremely enhanced. To get fine correction of wafer field CD uniformity, we have developed various methods to get close correlation of mask and wafer field CD uniformity by SEM, scatterometry and area CD methods. Especially, area CD from CD-SEM and optical CD measurement tools are developed to represent each area of masks. By optimizing measurement methods, repeatability and correlation of CD uniformity between masks and wafers are enhanced to get more than 0.7 of correlation between mask and wafer. And these give us the correction method to compensate field CD variation of maskCD on wafer. More than mask CD uniformity requirement on 65nm tech of DRAM memory device has been achieved.
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Today a remaining challenge is to determine the structural defect density (SDD) on a whole 156 x 156 mm2 multicrystalline (mc) silicon wafer over a timescale of a few minutes. In this contribution a new method is introduced to determine the SDD on large scale mc-Si wafers. The main advantage of the method presented is the possibility to obtain a complete map of the SDD of a 156 x 156 mm2 mc-Si wafer as well as a quantitative SDD analysis of the wafer in just a few minutes. Furthermore, the simple and quick sample preparation as well as the application of standard measurement equipment results in a convenient and cost-effective analysis tool. With these advantages, analysis of SDDs on large quantities of wafers, e.g. across the ingot height or width, can be easily realized in a few hours.
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In this paper, we present the experimental results on wafer-to-wafer and within-wafer critical dimension (CD) control. It is known that photoresist thickness affects CD. In this paper, we control photoresist thickness to control CD. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real time and makes use of the current wafer information for control of the current wafer CD. The experiments demonstrate that such an approach can reduce CD nonuniformity wafer to wafer and within wafer.
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