High thermal stability of doped oxide semiconductor for monolithic 3D integration
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a-Si TFTの技術動向のひとつは, ますます大型化・高精細化するアクティブマトリクス液晶ディスプレイへの対応である.特にデバイス性能面からTFT特性の向上, そして生産面からはスループットの向上が大きな課題であろう.この論文では, 次世代技術として最も重要と考えられる, 次の3つの要素技術につき, それらの効果と課題を議論する.(1) TFT特性の高性能化のための自己整合型TFT構造, (2) 自己整合型TFTに必要なプロセス技術としての非質量分離型イオン注入法, および (3) 大型基板の生産性向上のためのa-Si高速成膜技術.もちろん, これらは大型・高精細に限らず, すべてのTFT-LCDに適用しうる.いずれもまだ研究の緒についたばかりであるが, この分野に与える効果は大きく, また期待される技術であろう.
Oxide thin-film transistor
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Amorphous silicon–indium–zinc–oxide (a-SIZO) thin film transistor (TFT) was investigated with the process temperature below 150 °C. The a-SIZO TFT exhibited a field effect mobility of 21.6 cm2/V s and an on/off ratio of 107. The stabilities of a-SIZO TFT and indium–zinc–oxide (IZO) TFT were compared, and a-SIZO TFT showed 3.7 V shift for threshold voltage (Vth) compared to 10.8 V shift in IZO TFT after bias temperature stress. Si incorporation into IZO-system as a stabilizer, which was confirmed by x-ray photoelectron spectroscopy, resulted in small shift in Vth in a-SIZO TFT without deteriorating mobility of higher than 21.6 cm2/V s.
Oxide thin-film transistor
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본 논문에서는 저온 poly-Si(LTPS) TFT (thin film transistors)를 이용한 저소비전력 레엘 쉬프터 회로를 제안하였다. 제안한 레벨 쉬프터 회로는 capacitive-coupled 구조로, 기존의 cross-coupled 구조의 레벨 쉬프터 회로에 비해 더 적은 단락 전류와 더 짧은 지연시간을 갖는다. 또한 입력된 정신호와 부신호의 skew를 이용하여 동작하므로, 입력신호간의 skew가 문제가 되지 않는다. 제안한 레벨 쉬프터는 2인치 qVGA TFT-LCD 패널을 목표로 설계하였으며 소비전력은 약 7.2㎼/㎒이다. 전달지연시간은 7.8㎱, 면적은 67×36.5㎛²이다.
Oxide thin-film transistor
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Amorphous Hydrogenated Silicon (α-Si:H) has been a prevalent material in Thin Film Transistors (TFTs) since the inception of the technology. But due to their limited mobility they have been overhauled by alternative Amorphous Oxide Semiconductors (AOS). InGaZnO is one among them, which has variety of TFT applications. In this paper, simulation of two amorphous semiconductor TFTs have been carried out for analyzing their transport behavior and to compare the transport characteristics of the oxide TFTs. Simulation results reported that mobility have a high dependency on Urbach energy. Obtained maximum mobility 16 cm 2 /Vs from α-IGZO TFT is 73% higher than α-Si:H TFT. The results demonstrate the superiority of α-IGZO TFT mobility. The reported outcomes can advance the future oxide TFT Research and Development.
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Abstract The effect of hydrogen in the alumina gate insulator on the bottom gate oxide thin film transistor (TFT) with an InGaZnO film as the active layer was investigated. TFT with more H‐containing alumina films (TFT A) fabricated via atomic layer deposition using a water precursor showed higher stability under positive and negative bias stresses than that with less H‐containing alumina deposited using ozone (TFT B). While TFT A was affected by the pre‐vacuum annealing of GI, which resulted in Vth instability under NBS, TFT B did not show a difference after the pre‐vacuum annealing of GI. All the TFTs showed negative‐bias‐enhanced photo instability.
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【概要】 In-Ga-Zn-O(IGZO)に代表される非晶質酸化 物半導体は、高い電界効果移動度・大面積均一 性に優れることから、薄膜トランジスタ(TFT) のチャネル材料として期待されている[1]。し かしながら、レアメタル(In, Ga)は原産国が限 られ、埋蔵量も少ないため、価格高騰などの供 給リスクを抱えている。そこで、レアメタルフ リー材料である酸化亜鉛スズ(ZnSnO:ZTO)を チャネルに用いたTFTの作製を行った。また、 我々は、IGZO TFTにおいて、エッチストッパ ー(ES)層成膜条件により IGZO中の水素濃度が 変化し、TFT特性や信頼性が変化することを報 告している[2]。そこで、水素が、ZTO TFTの 特性に与える影響に関して研究を行った。 【実験】 本研究では Fig. 1に示す、ES層を有するボ トムゲート型 ZTO TFTを作製した。ES層には シラン(SiH4)・亜酸化窒素(N2O)・窒素(N2)を原 料ガスとした、プラズマ支援化学気相堆積 (PE-CVD)法により成膜した酸化シリコン (SiOx)膜を用いた。ZTOチャネル中での水素濃 度が TFT 特性に及ぼす影響を調べるため、ES 層成膜時の SiH4 ガス分圧(P[SiH4])を変化させ た TFTを作製し、特性評価を行った。
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With the development of the virtual reality and augmented reality displays, ultra-high resolution displays become one of the big concerns. People would not be bothered by display pixels when taking closer look at display with the resolution higher than 2000 ppi. The most important factor in the ultra-high resolution display is the pixel area and the smallest TFT size would be the first criteria in the TFT point of view. Although back channel etch (BCE) TFT and self-aligned (SA) TFT have been used for driving high resolution LCD and OLED, respectively, typical planar structured TFT would not permit display with ultra-high resolution. The vertical TFT with the smallest pixel pitch value among the TFT structures is suitable candidate. Furthermore, channel length of the vertical TFT can be precisely controlled by the thin film thickness of spacer. This results in high and uniform on-current of TFT. Meanwhile, vertical TFT can also provide channel length longer than the sub-pixel length. When we have to apply high gate voltage depending on the display mode, TFT with longer channel length within smaller sub-pixel size would be necessary. One of the advantages of oxide TFTs lies in the freedom of selection of architecture, materials, and process depending on the device application. Considering the main issue in the vertical TFT, the step coverage of active layer, oxide TFT seems to be the best selection. Oxide semiconductor and gate insulator used for the oxide TFT can be deposited by means of plasma enhanced atomic layer deposition (PEALD), which provides excellent step coverage of films. One of the issues in vertical oxide TFT is the relatively high off-current depending on the mobility of TFT due to the short channel length. Here, we compare the performance of vertical oxide TFTs with the variation of semiconductor’s carrier density. By virtue of the easiness for the modifying carrier concentration of InOx based semiconductor, we could adjust the mobility of vertical TFT with low off-current. Vertical TFT with InOx shows 1.26 mA at Vg = 5 V and Vds = 2.1 V, S.S of 0.14 V/dec., on/off ratio of 10 7 , and Von of -1.8V. Meanwhile at the same driving condition, IGZO shows on-current of 0.23 mA, S.S of 0.12 V/dec., on/off ratio of 10 8 and Von of -0.2V. We will discuss the best selection for the channel layer of vertical TFT depending on the display mode and show the optimized TFT performance depending on the carrier concentration of semiconductors.
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a-Si(amorphous silicon) TFT(thin film transistor)는 TFT-LCD(liquid crystal display)의 화소 스위칭(switching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 ASG(amorphous silicon gate) 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압(Vth)의 이동이다. 특히 고온에서는 문턱 전압의(Vth) 이동이 가속화 되고, Ioff current가 중가 하게 되고, 저온(0℃)에서는 전류 구동능력이 상온(25℃) 상태에서 같은 게이트 전압(Vg)에 대해서 50% 수준으로 감소하게 된다. 특히 ASG 회로는 여러 개의 TFT로 구성되는데, 각각의 TFT가 고온에서 Vth shift 값이 다르게 되어 설계시 예상하지 못한 고온에서의 화면 무너짐 현상 즉 고온 노이즈 불량이 발생 할 수 있다. 고온 노이즈 불량은 고온에서의 각 TFT의 문턱전압 및 I D -V G 특성을 측정한 결과 고온 노이즈 불량에 영향을 주는 인자가 TFT의 width와 기생 capacitor비 hold TFT width가 영향을 주는 것으로 실험 및 시뮬레이션 결과 확인이 되었다. 발생 mechanism은 ASG 회로는 AC 구동을 하기 때문에 Voff 전위에 ripple이 발생 되는데 특히 고온에서 ripple이 크게 증가하여 출력 signal에 영향을 주어 불량이 발생하는 것을 규명하였다.
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