Top-Gate Short Channel Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors with Sub-1.2 nm Equivalent Oxide Thickness
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Abstract:
We report high performance top-gate amorphous Indium-Gallium-Zinc-Oxide thin film transistors (α-IGZO TFTs) featuring the smallest equivalent oxide thickness (EOT) of sub-1.2 nm among all IGZO-channel TFTs, achieving the highest extrinsic peak transconductance (G m,ext ) of 62 μS/μm at a drain to source voltage (V DS )=2V(33.4μS/μm at V DS =1V) and excellent drain induced barrier lowering (DIBL) of 17.6 m V/V, for a device with a channel length (L CH ) of 160 nm. The best long channel device has a subthreshold swing (SS) of 67.5 mV/decade. This was enabled by using an ultra-scaled 5 nm high-k HfO 2 as the gate dielectric. In addition, temperature study was also performed on α-IGZO TFTs. Field effect mobility (μ eff ) show negligible degradation at high temperature, indicating the great potential of α-IGZO TFTs for various emerging applications.Keywords:
Transconductance
In this paper, we proposed a novel voltage-programmed pixel circuit based on amorphous indium gallium zinc-oxide thin-film transistor (a-InGaZnO TFT) for active-matrix organic light-emitting display (AMOLED) with an enhanced electrical stability and uniformity. Through an extensive simulation work based on a-InGaZnO TFT and OLED experimental data, we confirm that the proposed pixel circuit can compensate for both mobility variation and threshold voltage shift of the driving TFT.
AMOLED
Oxide thin-film transistor
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Field effect
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Hot-electron-induced degradation of transconductance and of threshold voltage at 77 K of n-channel enhancement metal-gate MOSFET's was investigated as a function of electrical stress applied at liquid nitrogen temperature. After stress, the threshold voltage was found to have increased at low drain voltages but to have remained unchanged at higher drain voltages, and the saturation transconductance was virtually unchanged for operation in the normal mode. For operation in the inverse mode (source and drain interchanged), the threshold voltage was found to have increased, independent of drain voltage, while the saturation transconductance was decreased. The threshold voltage for inverted operation increased monotonically with stress time, while the saturation transconductance decreased initially and then saturated. This saturation corresponds to an order of magnitude decrease in carrier mobility in the channel near the drain. These results are interpreted using a model in which the threshold voltage and channel mobility are position-dependent. While hot-electron-induced degradation may not be a problem for devices operated only in the forward saturation region, it could be a serious problem for devices such as bilateral switches.
Transconductance
Saturation (graph theory)
Overdrive voltage
Negative-bias temperature instability
Drain-induced barrier lowering
Saturation current
Electron Mobility
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In this paper, we study the effect of the drain voltage on the threshold voltage extraction in long-channel MOSFETs by the transconductance change and transconductance-to-current ratio change methods, using analytical modeling and experimental data obtained on advanced UTB SOI MOSFETs. It is shown that, although these two methods have the same physical background, they feature radically different behaviors with respect to the drain voltage effect. In particular, the transconductance change method yields a threshold voltage value, which regularly increases with drain voltage, and interpretation, as well as analytical expression for this dependence, is provided. In contrast, for the transconductance-to-current ratio change method, the increase of the extracted threshold voltage value with drain voltage is smaller and rapidly saturates; hence, the threshold voltage extraction is more stable and reliable. Modeling derivations are found to be in excellent agreement with measurements on long-channel UTB SOI MOSFETs as well as 2-D simulations.
Transconductance
Negative-bias temperature instability
Drain-induced barrier lowering
Overdrive voltage
Channel length modulation
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In this work, the carrier microscopic transport process of biaxial strained Si p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) under γ -ray radiation has been studied. Effect of γ-ray on devices and the relationship between the variation of device electrical characteristics and the total dose are investigated. A model for considering the degradation of threshold voltage and transconductance due to the total dose radiation is established. Based on this model, numerical simulation has been carried out. Results show that the threshold voltage of PMOSFET decreases with increasing radiation dose. At a lower total dose, the threshold voltage decreases linearly. However, at a higher total dose, it becomes saturated. The degradation can be explained by the generation of trapped charges which increase the impact possibility of carriers in the channel and induce the reduction of mobility and transconductance accordingly. Finally, the simulation results are compared with the experimental data. A good agreement is observed, indicating the validation of our proposed model.
Transconductance
Reverse short-channel effect
Negative-bias temperature instability
Electron Mobility
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The total ionizing dose response of bulk nFinFETs with multiple gate lengths and multiple fins is investigated for on-state bias condition. Experiments and Technology Computer Aided Design simulations were performed to analyze the effect of the trapped charges in the gate oxide and shallow trench isolation (STI) oxide on the threshold voltage and transconductance of the devices. The increases in the threshold voltage and transconductance are observed after X-ray irradiation. The positive shift of the threshold voltage is caused by the net negative charges trapped in the gate oxide. The simulation results show that the trapped holes in the STI oxide reduce the electric field and increase the electron mobility in channel near the fin bottom, which is the major contribution to the increased transconductance. An interesting phenomenon was also observed that the threshold voltage continues to increase during the annealing process, whereas the transconductance decreases. These results suggest that there may also be a small amount of trapped holes in gate oxide during irradiation, and those trapped holes are compensated by electrons transporting from the silicon during the anneal, leading to further positive shift of the threshold voltage. Moreover, the decrease in transconductance is mainly introduced by the neutralization of the trapped holes at STI/silicon interface.
Transconductance
Shallow trench isolation
Negative-bias temperature instability
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Transconductance
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In this paper, we proposed a novel voltage-programmed pixel circuit based on amorphous indium gallium zinc oxide thin-film transistor (a-InGaZnO TFT) for active-matrix organic light-emitting display (AMOLED) with an enhanced electrical stability and uniformity. Through an extensive simulation work based on a-InGaZnO TFT and OLED experimental data, we confirm that the proposed pixel circuit can compensate for both mobility variation and threshold voltage shift of the driving TFT.
AMOLED
Oxide thin-film transistor
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Abstract Short‐channel, high‐mobility organic transistors have been demonstrated using alkylated dinaphthothienothiophene. The field‐effect mobility for a transistor with a channel length of 2 mm was 1.46 cm 2 /Vs at operation of –15 V. The transconductance of the transistor reached to 500 µS/mm, which is one of the highest values in p‐channel organic transistors. The high mobility in short‐channel transistors is attributed to low contact resistance caused by Au/AuNi electrodes modified with pentafluorobenzenethiol. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)
Transconductance
Contact resistance
Electron Mobility
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This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.
Transconductance
Subthreshold conduction
Subthreshold slope
Negative-bias temperature instability
Atmospheric temperature range
Temperature coefficient
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