Network cache system with the autonomic recovery mechanism for wide-area SAN
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As multi-core trends are becoming dominant, cache structures are being sophisticated and complicated. Also, the bigger shared level-2 (L2) caches are demanded for higher cache performance. However, the big cache size is directly related to the area and power consumption. Designing a cache memory, one of the easiest ways to increase the performance is doubling the cache size. In mobile processors, however, simple increase of the cache size may significantly affect its chip area and power. To address this issue, in this paper, we propose the hy-way cache (hybrid-way cache) which is a composite cache mechanism to maximize cache performance within a given cache size. This mechanism can improve cache performance without increasing cache size and set associativity by emphasizing the utilization of primary way(s) and pseudo-associativity. Based on our experiments with the sampled SPEC CPU2000 workload, the proposed cache mechanism shows the remarkable reduction in cache misses with the penalty of additional hardware cost and additional power consumption. The variation of performance improvement depends on cache size and set associativity, but the proposed scheme shows more sensitivity to cache size increase than set associativity increase.
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The storage traffic for different logical units (LUs) of a disk array converge at the array's cache. The cache is allocated among the LUs approximately according to their relative I/O rates. In the case of nonuniform I/O rates and sensitivity to storage response times between differing applications in a storage area network (SAN), undesirable cache interference between LUs can result in unacceptable storage performance for some LUs. This paper describes SANBoost, a SAN-level caching approach that can be enabled selectively on a per-LU basis to provide a performance isolation mechanism for response time metrics related to storage quality of service (QoS). SANBoost automates hot data detection and migration processes in block-level storage. The design consists of a migration module implemented in a fabric-based SAN virtualization appliance and a solid-state disk (SSD) that acts as a cache resource within the same SAN. Simulation results quantify the impact of a specific static SANBoost caching policy on the SPC-1 benchmark workload and address the relative impact of adapting a threshold in the placement algorithm.
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This work presents a new hardware cache management approach for improving the cache hit ratio and reducing the bus traffic. Increasing the L1 cache hit ratio is a crucial aspect of obtaining good performance with the current processors. The proposed approach also increases the overall (L1 plus L2) cache hit ratio, especially in multiprocessor systems, where the bus latencies are low. This work focuses in multiprocessor systems where a forth kind of miss (the coherence miss) and the bus utilization problem appear; however, the model can also be applied to uniprocessor systems. Our organization increases the overall cache hit ratio and thus reduces the bus utilization. The proposed model introduces two independent L1 caches with different organizations placed in parallel. Each cache block has attached to it a small counter for storing the reuse related information. The proposed microarchitecture not only reduces the bus traffic and speeds up better than the conventional organization, but it also saves die area. The performance (versus conventional cache organizations) increases as the number of processors increases.
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With the dramatic increase in network speed during the past ten years, network processing efficiency has been significantly decreased. In this paper, we propose a network accelerating scheme, which employs cache locking method to reduce data and instruction accessing latency. Interrupts handling and buffer maintenance overheads are obviously decreased. Experimental results show that our solution increases about 22% network bandwidth and reduces 10% latency.
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Based on analyzing the current data of cache technology, a new cache network is produced. also the architecture and algorithm are proposed.
Cache invalidation
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This paper studies the influences of cache policies under SAN infrastructure and proposes a new kind of cache policyunified distributed memory cache management policy(UDMCMP) which utilizes high bandwidth provided by SAN and memory capacity of each clients to improve system performance, availability and scalability.
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In advanced multimedia communication based systems, performance improvement is one of the most important issues. Data cache consumes a major portion of the whole processor power for communication applications as they are mainly data intensive. The cache architecture cannot be taken care of specifically for an application in case of an integrated communication system. As a result, a big amount of cache memory is not used. In this paper, the software-controlled cache architecture has been proposed, that improves the energy efficiency of the shared cache in an integrated communication based system. For different cache regions, data types are allocated for an application. Only the allocated cache regions are activated. The effectiveness of software-controlled cache after integration is tested in a communication based System on chip. The results show the performance improvement of the system on chip up-to a huge level on ARM-like cache architecture.
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