Vertical Channel Capacitor-less One-Transistor DRAMs with a pass-way Trench for improving Retention Time
Ting-Pi HsuJyi-Tsong LinChih-Kai HuangChih-Chia LinAbhinav KrantiCyuan-You YuTing-Chung ChangPo-Hsieh Lin
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Abstract:
In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and writing time are investigated. The pass-way trench improves programming window and retention time of the structure in comparison to conventional structure.Keywords:
Dram
Data retention
Retention time
Dram
Position (finance)
Dynamic random-access memory
Shallow trench isolation
Interposer
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Due to increasing levels of integration, it is expected that next generation DRAMs will make use of trench capacitors to minimize the area of a cell. In this paper we examine the properties of oxides grown in trenches and compare them with comparable oxides grown on planar surfaces. We also examine the effects of various cell to cell spacing on the trench to trench leakage. We conclude that despite the challenges of trench technology, it is excellent for use in 1Mbit and 4Mbit DRAMS.
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Leakage (economics)
Shallow trench isolation
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Out from various cell concepts under investigation for the 16 and 64 Megabit DRAM generation the depletic type trench cell is still favoured because of its low process complexity. However, further shrinking of this cell concept, which is been widely used for the 4 Megabit DRAM, may result in leakage problems between neighbouring trench capacitors. The isolation of a modified version of this cell type, the SSP cell, has been investigated by numerical simulation as a function of well implantation dose and the trench to trench separation in the case of three closely spaced trench capacitors.
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Megabit
Shallow trench isolation
Leakage (economics)
Dynamic random-access memory
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As DRAM cells continue to shrink, they become more susceptible to retention failures. DRAM cells that permanently exhibit short retention times are fairly easy to identify and repair through the use of memory tests and row and column redundancy. However, the retention time of many cells may vary over time due to a property called Variable Retention Time (VRT). Since these cells intermittently transition between failing and non-failing states, they are particularly difficult to identify through memory tests alone. In addition, the high temperature packaging process may aggravate this problem as the susceptibility of cells to VRT increases after the assembly of DRAM chips. A promising alternative to manufacture-time testing is to detect and mitigate retention failures after the system has become operational. Such a system would require mechanisms to detect and mitigate retention failures in the field, but would be responsive to retention failures introduced after system assembly and could dramatically reduce the cost of testing, enabling much longer tests than are practical with manufacturer testing equipment.
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Data retention
Retention time
Dynamic random-access memory
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Dram
Data retention
Leakage (economics)
Retention time
Dynamic random-access memory
Trap (plumbing)
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This paper presents a multiscale physics-based approach for evaluating DRAM cell retention time including variable retention time effects. The flow goes from ab-initio DFT simulation to high-sigma SPICE analysis, allowing for the evaluation of the causes and retention time related failure states for DRAM technologies.
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Data retention
Retention time
Spice
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Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it is still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition. As these failures could be related to the memory cell's ability to retain its stored charge, an empirical characterization of DRAM data retention time was performed within this study. Retention time information was collected from SDRAM devices from two different vendors to evaluate the impact of four different factors (temperature, data background, previous charge level and variable retention time) on DRAM cells retention time. Gathered results can be useful in defining enhanced test procedures for the early detection of data retention faults.
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Data retention
Dynamic random-access memory
Universal Memory
CAS latency
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As design rule shrinking, it's more challenged to keep the enough capacitance for DRAM device requirement. For deep trench DRAM, one of methods supplied enough capacitance of providing deeper trench. Currently, the trench depth is over 6 mum for the 512M DRAM. In order to meet this stringent requirement, we need to care about not only the profile of deep trench (DT) but also the enough depth. Due to this high aspect ratio process is roughly over 60, it is very difficult for current inline defect monitor's method to check the abnormal trench profile. Traditional methods for verifying DT profile must destroy the wafer by the physical failure analysis. The wafer is analyzed by SEM (scanning electron microscope) to check DT cross-section or FIB (focus ion beam) to inspect slice view image. These methods provide difficultly the whole wafer map message for DT profile, offering merely random-cross-section inspection. Now we provide an inline-fast-effective method by the IR spectrum's analysis that can give the available message to monitor the DT profile
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We present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 48nm node. The key technology enablers are a new cell architecture "Wordline over Bitline" (WOB) realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery devices at reduced internal voltage, and the integration of a MIC/ HfSiO trench capacitor.
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Shallow trench isolation
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A charge offset scanning method of determining individual cell leakages in DRAM devices is described. The leakage behaviour of cells from the main and tail distributions is compared and the results of data retention studies on a 0.5µm CMOS embedded DRAM technology for ASIC applications are also discussed. An order of magnitude improvement in the retention time of the tail bits was achieved as an outcome of the study.
Data retention
Dram
Leakage (economics)
Retention time
Application-specific integrated circuit
Dynamic random-access memory
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