Batch Fabrication of Silicon Micropumps
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Die preparation
Wafer backgrinding
Wafer testing
Wafer Bonding
Wafer fabrication
After the patterning and probe process of wafer have been achieved, the dicing processing is necessary to separate chips from a wafer. The dicing process cuts a semiconductor wafer to lengthwise and crosswise directions to make many chips. The existing general dicing method is the mechanical cutting using a narrow circular rotating blade impregnated diamond particles or laser cutting. Inferior goods can be made by the mechanical or laser cutting unless several parameters such as blade, wafer, cutting water and cutting conditions are properly set. Moreover, we can not apply these general dicing method to that of GaN wafer, because the GaN wafer is harder than general semiconductor wafers such as GaAs, GaAsP, AIGaAs and so forth. In order to overcome these problems, this paper describes a new wafer dicing method using fixed diamond scriber and precision servo mechanism.
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This paper describes the new wafer level packaging process with the diced chip array on the small-diameter handling wafer. The general purpose of wafer level packaging is to realize a smaller, more functional and cost effective electronic package. For example, Wafer Level chip size package and Wafer stacking 3D package are the most effective packaging processes/structures using semiconductor wafer process. In the semiconductor industrial trend, silicon wafer sizes become larger to achieve a higher chip throughput and to reduce a chip cost. However in actual applications, the packaging needs are diversified and the required number of each package type does not meet the huge sized wafer processing. In this paper, we introduce the new packaging technique. In this new technique, after dicing CMOS wafer to the individual chips, we rearrange them on another smaller handling wafer. We, then, planarize the surface after filling up the resin on it, which can be used just like a single wafer. As the result, we can have a free hand to choose the size of handling wafer, and it means that we can use the existing equipment, which leads to lower cost and shorter development time. First, the influence of residual stress after rearranging the matrix of chip on the handling wafer was investigated with using FEM-modeling. It was found that the both of the sell size of the matrix and the material properties of the filled resin greatly influence on the wafer warpage, and that the design of matrix and the material of resin are key to complete the process of this new technique. Second, we tried to apply this new technique to an image sensor. 8×8 matrix of 9mm 2 CMOS image sensor chips are rearranged on 4inch glass wafer, and we fabricated TSVs in the image sensor chips for chip size package.
Wafer backgrinding
Die preparation
Wafer testing
Wafer-level packaging
Wafer-scale integration
Semiconductor device fabrication
Chip-scale package
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In this paper characterization and qualification methods of wafer- bonded MEMS devices are introduced. The main focus is on stud pull tests for bond strength measurement in real MEMS chips, in combination with a statistical Weibull diagram evaluation. The stud pull test covers all strength-related aspects from wafer bonding and dicing as well as from the whole wafer process and final dicing. Based on the results of this test, it was possible to optimize the wafer bonding quality regarding strength, and subsequently it was used to qualify the reliability of different wafer bonding techniques in complete MEMS technologies. In addition, the hermeticity of the wafer-bonding interface was tested and qualified by assessing the functionality of MEMS devices requiring hermetic sealing of a low pressure or vacuum.
Die preparation
Wafer backgrinding
Wafer testing
Wafer Bonding
Bonding strength
Characterization
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Micro-electro mechanical systems (MEMS) are used being combined with integrated circuit or large scale integration (LSI) in many cases. The heterogeneous integration can be performed by wafer transfer of multiple MEMS on a carrier wafer to an LSI wafer. The wafer transfer methods for the MEMS on LSI can be categorized as film transfer, device transfer (via-last), and device transfer (via-first). The heterogeneous integration using the wafer level transfer or the chip level wafer transfer can be used to fabricate key components for such systems. Lead zirconate titanate actuated MEMS switches were fabricated on an LSI wafer. The piezoelectric MEMS switch works at lower driving voltage and occupies smaller area than electrostatic MEMS switches. Digital fabrication of LSI based on maskless lithography is expected for cost-effective small-volume production and short-term development. The MEMS wafer is bonded to a glass carrier wafer using bonding interlayer, and grooves are made on the MEMS wafer by dicing.
Wafer backgrinding
Die preparation
Wafer Bonding
Wafer-level packaging
Wafer testing
Lead zirconate titanate
Wafer-scale integration
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The wafer-level packaging of an electrostatic Si microgripper was investigated. It is important to ensure safe handling and freedom from damage during fabrication and assembly of micro devices. Some reliability problems have occurred during packaging or handling of the microgripper, regardless of actuation principles. After pre-release of the sacrificial layer, a new wafer-level packaging was processed by anodic bonding between a glass wafer with through-holes and a Si wafer device. A laser dicing has been performed before wire bonding for freedom from damage during both dicing and packaging processes. After the laser dicing, post-releasing has been done. The diced chips were actuated by applied voltage from 0 V/sub dc/ to 15 V/sub dc/. The jaws of the fabricated microgripper have been actuated from 0 /spl mu/m to 25 /spl mu/m.
Die preparation
Wafer Bonding
Wafer-level packaging
Wafer backgrinding
Wafer testing
Electronic Packaging
Wafer fabrication
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The ecomony scale of return for semiconductor wafers can be attributed to 2 factors i.e.1) number of systems that is crammed onto a wafer and 2) substitution of precious metal (Au) to other material for the wafer backmetal. Any of these 2 changes will be a major challenge to semiconductor wafer dicing yield. Crack die with a random order is a great myth to be dicovered. In this study, Moire Techniques is being adopted to perform the upfront analysis on the crack die to minimize the yield loss during dicing process. In this study we focus and to corellate 3 different wafers with different size (5", 6" and 8") and backmetal (bare silicon, Au and AuX). The effect of the backside metallization to the die strength has been numerically and experimentally investigated. These results obtained is being made to optimise the dicing method to obtain a homogenous stresses across the wafer.
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Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.
Die preparation
Wafer backgrinding
Wafer testing
Flatness (cosmology)
Wafer Bonding
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This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.
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A new wafer capping process is investigated in this study. The objective of this study is to come out a simple and low cost wafer capping process to make the capped MEMS device wafers “transparent” to traditional IC assembly processes. The carrier wafers with metal mini-caps are bonded on the MEMS device wafers through solder bonding, and the mini-caps are then transferred and left on the MEMS device wafer through a selective etching of the carrier wafers. The metal mini-cap capped device wafers are virtually of the same thickness as original ones; in addition, the transferred metal mini-caps provide a mechanical protection to the MEMS devices during the consequent assembly processes such as wafer dicing, die bonding, molding, etc. With an additional design of 2nd level interconnection on the mini-cap carrier wafer, the transferred MEMS device wafers can be singulated and become a wafer level package with compliant leads.
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Wafer testing
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Wafer Bonding
Wafer-level packaging
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In this study, thin wafer handling of 300mm wafer for 3D IC Integration is investigated. Emphasis is placed on the determination of the effect of a dicing tape on thin-wafer handling of wafers with Cu-Au pads, Cu-Ni-Au UBM, and TSV interposer with RDL. Also, thin-wafer handling critical issues such as the chip/interposer wafer, carrier wafer, temporary bonding, thinning, backside process, de-bonding, and assembly are presented and their potential solutions are discussed. Finally, state-of-the-art of materials and equipments for thin-wafer handling are examined.
Die preparation
Wafer backgrinding
Interposer
Wafer testing
Wafer Bonding
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