BETSY: synthesizing circuits for a specified BIST environment
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Abstract:
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable SYnthesis) for synthesizing circuits that achieve complete (100%) fault coverage in a user specified BIST environment. Instead of optimizing the circuit for a generic pseudo-random test pattern generator (by maximizing its random pattern testability), the circuit is optimized for a specific test pattern generator, e.g., an LFSR with a specific characteristic polynomial and initial seed. This solves the problem of having to estimate fault detection probabilities during synthesis and guarantees that the resulting circuit achieves 100% fault coverage. BETSY considers the exact set of patterns that will be applied to the circuit during BIST and applies various transformations to generate an implementation that is fully tested by those patterns. When needed, BETSY inserts test points early in the synthesis process in an optimal way and accounts for them in satisfying timing constraints and other synthesis criteria. Experimental results are shown which demonstrate the benefits of optimizing a circuit for a particular test pattern generator.Keywords:
Built-in self-test
Digital pattern generator
Scan based built in self test (BIST), which naturally extends scan based test methodology with test patterns applied from test equipment to BIST, can be used for the self test of sequential circuits and attain higher fault coverage. If the circuit under test (CUT) contains multiple parallel scan chains, a parallel generator is needed. Known as the common pseudo random pattern generator (PRPG), an LFSR can be configured to generate a random pattern stream. The PRPG based patterns may be applied to the existing scan architecture directly from the LFSR, or through some decorrelation logic. In order to attain higher fault coverage, it is very important to analyze the test pattern generation in the scan based BIST. The paper presents a kind of scheme for test pattern generation in the scan based BIST for the circuits with multiple scan chains. In the test pattern generation scheme the PRPG, which is implemented by an LFSR, shifts the sequences into all scan chains simultaneously. The correlativity weight R(M) of multiple scan chains is also defined in the paper. Based on the analysis of the different degree effect on fault coverage due to the different configuration of multiple scan chains, one conclusion is drawn that the probability that the fault coverage is reduced is increased with an increase of the correlativity weight R(M) . If the circuit is tested by the multiple scan chains with the minimum R(M) , the probability that the fault coverage is reduced is least. In the paper a method to construct multiple scan chains with minimum correlativity weight R(M) is proposed to overcome the bad effect on fault coverage due to the correlation between scan chains. Furthermore the minimum set of deterministic patterns is generated for hard to test faults by ATPG and the set is used to design the bit modifying logic circuit (BML), which is located between multiple scan chains and the CUT. Through BML the signals in multiple scan chains are controlled to input to the CUT. When the test control signal is low, the test patterns in multiple scan chains are input into the CUT directly. When the test control signal is high, the value of the signals at certain bit positions in the multiple scan chains are modified by BML and the changed test patterns are input into the CUT to test hard to test faults for complete fault coverage. The experiments on some ISCAS'89 benchmark circuits show that the complete fault coverage can be obtained by the test method presented by the paper. The overhead of BML is also analyzed.
Scan chain
Built-in self-test
Test compression
Digital pattern generator
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Test generation for highly s equential circuits is quite complex so sequential circuits must be designed for testability to obtain good fault coverage and reduce test generation costs. A ne w testability measure based on the conflict analysis of hard-to-detect faults in the test generation process was used to develop a two-stage non-scan design for testability method. The new testability measure emulates most general featu res of sequential automatic test pattern generation (ATPG). The method was run o n a number of ISCAS benchmarks. The test results show that the proposed method p rovides better fault coverage and test efficiency than two recent non-scan desi gns for testability methods.
Design for testing
Test compression
Code coverage
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A low-power test pattern generation, named the low switching activity test pattern generation (LSA-TPG), is proposed to reduce the power dissipation of built-in self-test (BIST)-based circuits during test. A single input changing (SIC) test pattern is generated by a counter and a Gray encoder which is called the SICG (single input changing generator). The built-in test vectors are generated by the SIC patterns which are exclusive-ORed with seeds generated by the modified linear feedback shift register (LFSR). All the test vectors are SIC patterns during the 2m test clock period; thus the switching activities of the test vectors are greatly reduced in test mode without compromising fault coverage. The proposed structure has the advantages of low test power and low hardware overhead. LSA-TPG is independent of circuit under test (CUT) and flexible enough to be used in both BIST and scan-based BIST architectures. The proposed architecture increases the correlation among the test patterns with negligible impact on test length. Experiments conducted on ISCAS'89 benchmark circuits demonstrate that the proposed scheme gives better fault coverage with a large reduction in test power dissipation.
Built-in self-test
Test compression
Digital pattern generator
Benchmark (surveying)
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Deterministic testing is by far the most interesting Built-in Self-Test (BIST) technique due to the minimal number of test patterns it requires and to its predefined fault coverage. However, such a technique is not applicable since despite their efficiency the existing deterministic test pattern generators are enormous consumers of overhead silicon area. Therefore, we propose a mixed test scheme which consists in applying to the circuit under test, a pseudo-random test sequence followed by a deterministic one obtained from an ATPG tool. This scheme allows a maximal fault coverage detection to be achieved for complex and realistic faults, e.g. stuck-at, stuck-open or delay faults, moreover, the silicon area overhead of the mixed hardware generator is drastically reduced. A compromise is to be found between the silicon area overhead of this generator and a slightly longer mixed test sequence. As an example, the additional circuitry requirements of the mixed test pattern hardware generator for the C3540 circuit are reduced to 20% of the nominal chip size for a total set of 1000 mixed test patterns. >
Built-in self-test
Digital pattern generator
Test compression
Code coverage
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This paper presents a new effective BIST scheme that achieves 100% fault coverage with low hardware overhead, and without any mollification of the circuit under test, i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator (e.g. an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very simply and with low silicon area cost, without the need of any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length.
Digital pattern generator
Sequence (biology)
Built-in self-test
Sequential logic
Test compression
Combinational logic
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We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed test application. We introduce a uniform, parametrized structure for test pattern generation. By matching the parameters of the test pattern generator to the circuit-under-test, high fault coverage is achieved. In many cases, the fault coverage is equal to the fault coverage that can be achieved by deterministic test sequences. We also investigate a method to minimize the size of the test pattern generator, and study its effectiveness alone and in conjunction with the insertion of test-points.
Sequential logic
Built-in self-test
Digital pattern generator
Test compression
Code coverage
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We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed test application. We introduce a uniform, parametrized structure for test pattern generation. By matching the parameters of the test pattern generator to the circuit-under-test, high fault coverage is achieved. In many cases, the fault coverage is equal to the fault coverage that can be achieved by deterministic test sequences. We also investigate a method to minimize the size of the test pattern generator, and study its effectiveness alone and in conjunction with the insertion of test-points.
Sequential logic
Test compression
Built-in self-test
Digital pattern generator
Code coverage
Scan chain
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Built-In-Self-Test (BIST) has become one of the major test techniques for today's large scale and high speed designs. In this paper, a novel test pattern generator (TPG) for built-in-self-test is presented to attain the target fault coverage without increasing test length sequences. This proposed TPG method generates multiple patterns with single input change i.e., all vector applied to a scan chain is a single input change (SIC) vector. Hence, it reduces the number of transitions that occur at scan inputs during scan shift operations and also reduces the switching activity in the circuit under test (CUT). The linear feedback shift register (LFSR) is used to generate test patterns for primary inputs or scan chains input and a multiple input shift register (MISR) compresses test responses received from primary output or scan chains output. To test the fault coverage ratio of proposed test pattern generator a complicated Wallace tree multiplier circuit will be used as circuit under test and output response of Wallace tree multiplier is stored in LUT for error comparison. Simulation results with Wallace tree multiplier circuit demonstrate that MS IC can save test power by approximately 7% and achieves the target fault coverage by above 70% without increasing the test length sequences.
Test compression
Built-in self-test
Test vector
Scan chain
Digital pattern generator
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Problem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS’89 bench mark circuits.
Digital pattern generator
Built-in self-test
Test compression
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