MIC@R : A Generic Low Latency Router for On-Chip Networks
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The design of efficient router represents a key issue for the success of the Network-on-chip approach. This paper presents and evaluates a novel router architecture MIC@R suitable for Networks-on-Chip (NoC) Design. This router offers lowest latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using Fast Parallel Routing (FPR) arbitration that consists in parallel processing -in one stage, routing decisions and arbitration. The proposed router architecture is evaluated in 2D Mesh with two adaptive routing algorithms: fully adaptive (FA) and Proximity Congestion Awareness (PCA). The obtained results show that our router, combined with adaptive routing techniques is effective in terms of latency and throughput.Keywords:
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Network-on-Chip (NoC) router is an entity that facilitates communication between subsystem or IP cores on an integrated circuit. Faults such as permanent fault, transient fault and random fault are commonly observed on a NoC router. They may severely impact the functionality of an NoC router if not handled appropriately. This project proposes a mechanism to identify error and perform self-testing in NOC router by enhancing the Register Transfer Level (RTL) design of CONNECT NoC Baseline Router with error detection mechanism, as well as devising a built in selftest mode for NOC router. Both proposed error detection mechanism and built in self-test mode have been successfully implemented using System Verilog. The work presented in this project shows possible enhancement to NoC router architecture to detect erroneous packets. NoC router is able to detect faults through proposed error dection tecchniques. This allows router self-test in order to sustain the functionality of a system in the presence of faults. Simulation results show that additional logics do not affect NoC router performance
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Aggressive technology scaling into the deep nanometer regime has made the Network-on-Chip (NoC) in multicore architectures increasingly vulnerable to faults. This has accelerated the need for designing reliable NoCs. To this end, we propose a reliable NoC router architecture capable of tolerating multiple permanent faults. The proposed router achieves a better reliability without incurring too much area and power overhead as compared to the baseline NoC router or other fault-tolerant routers. Reliability analysis using Mean Time to Failure (MTTF) reveals that our proposed router is six times more reliable than the baseline NoC router (without protection). We also compare our proposed router with other existing fault-tolerant routers such as Bullet Proof, Vicis and RoCo using Silicon Protection Factor (SPF) as a metric. SPF analysis shows that our proposed router is more reliable than the mentioned existing fault tolerant routers. Hardware synthesis performed by Cadence Encounter RTL Compiler using commercial 45nm technology library shows that the correction circuitry incurs an area overhead of 31% and power overhead of 30%. Latency analysis on a 64-core mesh based NoC simulated using GEM5 and running SPLASH-2 and PARSEC benchmark application traffic shows that in the presence of multiple faults, our proposed router increases the overall latency by only 10% and 13% respectively while providing better reliability.
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To satisfy the requirement that the router in network on chip can support multiple IP cores,and its latency performance is good,a router with a distributed routing and arbitrating structure is designed.Its arbitration module arbitrates on the request state of the current router and the state of the input buffer in the next router,this arbitration method improves the success rate of the packet transmission,so it decreases the transmission latency and improves latency performance of the router,meanwhile the simulation results indicate the router has good expansibility in area overhead.
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A new solution to port general operating systems and their routing software to switch router is presented. The solution shields the architecture difference between traditional router and switch router to application level software, thus it may support general operating system and their routing software on switch router platform. The solution is also considered as requirements of both data communication and control functions. And same ways of the access and control of the router are provied as traditional router, so routing software of the general operating system may be ported to switch router platform rapidly with the upgradeable flexibility. Practical design approves that the solution has a good compatibility and flexibility.
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Technology scaling has led to the integration of many cores into a single chip. Multiprocessor Network-on-Chip (NoC) seems to be a good solution for the higher performance desired VLSI designs. The main challenge is how to enhance the communication efficiency in NoC. The NoC is a new paradigm which is fast emerging at present. The performance of the on-chip-networking depends on routing techniques used in the system. The existing techniques such as Round Robin Arbitration are not so efficient in finding an optimal path. The authors have chosen a different routing algorithm called Optimal Address Based Router (OAR) to find an optimal path which has low overhead. In this paper, we have reported a comparative evaluation of Optimal Address Based NoC router and Round Robin Arbitration based NoC router. The simulated results indicate that the Optimal Address Based NoC router is a better choice. The implementation is done on FPGA Spartan 3Xc 3s400 board. Further analyses of results shows that the optimal address based router consumes 71% lower power, occupies 90% less area and is faster by a factor of 35%.
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The first implementation of the cross-protect router is described in this chapter. Moreover, the results of tests of an XP router prototype conducted in a laboratory are presented. These results show the advantages of the XP router over the IP router. It is shown that traffic in FAN is served fairly and the packets of streaming flows are transmitted with high priority. Moreover, test results confirm that streaming flows are served with acceptable quality even in highly loaded links, which is not observed for the classic IP network. The tests also show several problems which were not caught by the simulation studies presented before. The tests ultimately show that Flow-Aware Networking works as a concept, and that, by reaching maturity, it is ready for large-scale deployment. As a software framework for the implementation the Click Modular Router environment which is widely used for building experimental software routers and switches was chosen.
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