Reducing pressure in bounded DBT code caches
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Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight constraints on memory and performance. A DBT uses a software-managed code cache to hold blocks of translated code. To minimize overhead, the code cache is usually large so blocks are translated once and never discarded. However, an embedded system may lack the resources for a large code cache. This constraint leads to significant slowdowns due to the retranslation of blocks prematurely discarded from a small code cache. This paper addresses the problem and shows how to impose a tight size bound on the code cache without performance loss. We show that about 70% of the code cache is consumed by instructions that the DBT introduces for its own purposes. Based on this observation, we propose novel techniques that reduce the amount of space required by DBT-injected code, leaving more room for actual application code and improving the miss ratio. We experimentally demonstrate that a bounded code cache can have performance on-par with an unbounded one.Keywords:
Cache pollution
Cache invalidation
Code (set theory)
Unreachable code
Smart Cache
Page cache
Dead code
Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and error prone, such optimization results in obfuscated code that is difficult to maintain and reuse. In this paper, we present a step towards code-size-aware compilation. We phrase register allocation and code generation as an integer linear programming problem where the upper bound on the code size can simply be expressed as an additional constraint. The resulting compiler, when applied to six commercial microcontroller programs, generates code nearly as compact as carefully crafted code.
Unreachable code
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Register allocation
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An instruction scheduler utilizes code reordering techniques for generating schedules in which instructions can be issued without delays. In order to perform code reordering across branches, code motion is performed that hoists some instructions above branches and sinks others below branches. Following code reordering, compensation code must be introduced in order to preserve program semantics. In this paper, we demonstrate that several important code optimizations can be performed as a side-effect of generating compensation code. These optimizations include partial redundancy elimination, partial dead code elimination, elimination of redundant loads and elimination of dead stores. We demonstrate how existing data-flow frameworks for these optimizations can be extended for generating optimized compensation code.
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Full web browsing with smart phones requires a high-performance JavaScript engine since JavaScript execution with a mobile CPU is slow. So, mobile JavaScript engines employ a just-in-time compiler (JITC), which translates JavaScript code to machine code at runtime. One issue is that since mobile phones suffer from tight memory constraints, the JITC needs to keep a low memory footprint by generating small-sized machine code. In fact, many mobile CPUs support half-sized encoding for small code size with small performance degradation, as in the ARM Thumb2. This paper describes our code generation and optimization for a mobile JavaScript JITC in the Webkit's SquirrelFish Extreme (SFX) for the ARM Thumb2. We try to generate as many 16-bit instructions as possible and reduce the data area, while strictly following the code generation guidelines of the SFX, which actually leaves little room for code optimization. Our experimental results show that we could reduce the code size by 29% with a performance degradation of 3.5%, compared to the ARM version of the SFX.
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E-Code is a higher-level language for dynamic code generation. E-Code specifically targets the dynamic generation of small code segments whose simplicity does not merit the complexity of a large interpreted environment. To that end, E-code is as simple and restricted a language as possible within the bounds of its target environment. E-Code’s dynamic code generation capabilities are based on DRISC, a Georgia Tech package that provides a programatic on-the-fly code generation through a virtual RISC instruction set. DRISC also has a “virtual register” mode in which it performs simple register allocation and assignment. E-Code consists primarily of a lexer, parser, semanticizer and code generator.
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Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and error-prone, such optimization results in obfuscated code which is difficult to maintain and reuse. In this paper, we present a code-size-directed compiler. We phrase register allocation and code generation as an integer linear programming problem where the upper bound on the code size can simply be expressed as an additional constraint. Our experiments show that our compiler, when applied to two commercial microcontroller programs, generates code as compact as carefully crafted code.
Unreachable code
Dead code
Dead code elimination
Code (set theory)
Register allocation
Cite
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Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and error-prone, such optimization results in obfuscated code which is difficult to maintain and reuse. In this paper, we present a code-size-directed compiler. We phrase register allocation and code generation as an integer linear programming problem where the upper bound on the code size can simply be expressed as an additional constraint. Our experiments show that our compiler, when applied to two commercial microcontroller programs, generates code as compact as carefully crafted code.
Unreachable code
Dead code
Dead code elimination
Code (set theory)
Register allocation
Cite
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Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and error-prone, such optimization results in obfuscated code which is difficult to maintain and reuse. In this paper, we present a code-size-directed compiler. We phrase register allocation and code generation as an integer linear programming problem where the upper bound on the code size can simply be expressed as an additional constraint. Our experiments show that our compiler, when applied to two commercial microcontroller programs, generates code as compact as carefully crafted code.
Unreachable code
Dead code
Dead code elimination
Code (set theory)
Register allocation
Cite
Citations (0)