BER estimation for serial links based on jitter spectrum and clock recovery characteristics
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Abstract:
High performance serial communication systems often require the bit error rate (BER) to be at the level of 10/sup -12/ or below. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems cost-effectively. We propose a new technique for accurate and efficient estimation of the BER. The proposed technique estimates the BER based on the spectral information of jitter and the characteristics of the clock and data recovery circuit. The method can significantly reduce the production test time for BER testing. Simulation results demonstrate the potential usefulness of the method.Keywords:
Data recovery
Clock Recovery
Spectral Efficiency
We propose a novel clock and data recovery method for high baud rate four-level pulse amplitude modulation format receivers without any digital signal processing. The new phase detector operates with a single sample per symbol and uses only high-speed logical circuits.
Baud
Clock Recovery
Modulation (music)
Data recovery
SIGNAL (programming language)
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Clock domain crossing
Clock Recovery
Data recovery
SIGNAL (programming language)
Digital clock manager
Limiting
Self-clocking signal
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A new phase lock loop (PLL) is proposed and demonstrated for clock recovery from an ultrahigh-speed time-division multiplexed (TDM) optical signal. A traveling-wave laser-diode amplifier (TW-LDA) is used as a phase detector, and the cross-correlation component between the optical signal and an optical clock pulse train is detected as a four-wave-mixing (FWM) signal generated in the TW-LDA. A timing clock from a TDM signal is extracted as a prescaled electrical clock, and this prescaled clock is directly recovered from a randomly modulated TDM optical signal. A prescaled 6.3 GHz clock is successfully extracted from a 100 Gb/s signal using the timing comparison output obtained as the cross-correlation between the optical signal and a short (<10 ps) 6.3 GHz optical clock pulse train in the generated FWM light. A comparison of the PLL phase noise with a previously reported gain modulation method is also shown, and the possibility of the Tbit/s operation of this PLL is also considered in the experiments.
Clock Recovery
SIGNAL (programming language)
Four-wave mixing
Laser diode
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A new baseband clock recovery algorithm for /spl pi//4-QPSK modulated signals is proposed. Conventionally the clock recovery methods with a non-data-aided algorithm for /spl pi//4-QPSK modulated signals are based on square devices and the jitter performance of those methods is usually worse than that of the clock recovery methods with a data-aided algorithm. However, the data-aided algorithm suffers from slow initial acquisition and is prone to the potential error accumulation. The proposed clock recovery method adopting a new non-data-aided algorithm shows jitter performance close to that of the data-aided ones, as well as removes the error accumulation problem and achieves fast clock recovery.
Clock Recovery
Data recovery
Carrier recovery
Digital clock manager
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We demonstrate an all-optical clock-and-data recovery technology for 10-Gb/s NRZ-DPSK signals. With a relatively simple configuration, the clock-recovery scheme achieves less than 1.5-ps RMS jitter for signals after fiber transmission. The pattern-dependence of data-recovery is within 0.5-dB at BER10 -9 .
Clock Recovery
Data recovery
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The amount of data transmitted over the global communications networks has experienced a dramatic increase over the last years, mainly driven by the exponential growth of the Internet. For this reason, increasingly faster and more reliable circuits are needed to allow a correct performance at speeds in the range of the Gbps. The superior power characteristics and overall performance make optical fiber the preferred choice to implement the channel in communications links, giving rise to the concept of optical communications. Due to their bandwidth limitations, in a typical optical communcations link data cannot be transmitted with a timing reference; the clock signal that allows its correct interpretation has to be extracted at the receiver in a block called clock and data recovery circuit (CDR). Typically, a CDR circuit is a closed-loop system that generates an oscillating signal capable of tracking the phase of the incoming data stream; as well, it uses the generated clock signal to regenerate the data stream, minimising the effects of non-idealities during transmission. This paper presents the design of a CDR circuit intended to meet the 10GBase-LX4 Ethernet specifications for continuous operation at 3.125 GHz, designed in a standard 0.18 m CMOS technology provided by UMC. A detailed description of the full CDR circuit and the different blocks taking part in it will be provided, emphasising the requirements that each of them must satisfy. Finally, the correct performance of the proposed CDR circuit will be analysed by means of an extensive set of post-layout simulations.
Clock Recovery
Data recovery
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A simple and robust prescaled clock recovery technique is analyzed and demonstrated. An electrical clock is extracted from an ultra-high-speed time-division multiplexed (TDM) RZ signal using a "classic" approach to clock recovery with a detector and a bandpass filter (BPF). A subharmonic tone at the base rate frequency is generated by inducing a small misalignment between adjacent pulses in the transmitted data. The subharmonic tone is recovered as a clock signal at the receiver. Numerical calculations clarify the effect of filter bandwidth, word length, and strength of timing shift on the received timing jitter. Furthermore, it is found numerically that correlated TDM channels will decrease the jitter of the recovered clock considerably. A clock recovery circuit is implemented into an experimental 40 Gb/s and 80 Gb/s optical TDM (O-TDM) system without any observed penalty. Measurements of the timing jitter of the recovered prescaled clock have been performed to verify the numerical results. A 10 GHz clock signal with subpicosecond root-mean-square timing jitter is recovered from a 40-Gb/s O-TDM sequence without a phase-locked loop (PLL) configuration. By using a PLL-configuration, the timing jitter is reduced further by 50%. A discussion on the influence on transmission capacity is performed in general and for nonlinear optical communication systems in particular.
Clock Recovery
CPU multiplier
Clock domain crossing
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Clock Recovery
Time-division multiplexing
SIGNAL (programming language)
Modulation (music)
Digital clock manager
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Clock Recovery
Self-clocking signal
SIGNAL (programming language)
Signal regeneration
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Clock recovery and decision circuit applied to optical fiber communication is investigated. GaAs decision circuit and clock recovery circuit fabricated with depletion-mode GaAs metal-semi- conductor field-effect transistors (MESFET's) has been designed. The base circuit cell of the de- cision circuit is source-coupled field-effect transistor logic (SCFL) circuit. The clock recovery cir- cuit contains a preprocessor and a phase-locked loop (PLL). It is proved by simulation analysis that the clock recovery circuit can recover 2.5GHz clock signal from the input and the 2.5Gbit/s decision circuit can deal with input signal rightly and produce correct digital output signal after being sampled by recovered clock. It is proved by test that the 2.5Gbit/s circuit can deal with input signal and produce output signal rightly after being sampled by recovered clock.
Clock Recovery
Asynchronous circuit
SIGNAL (programming language)
Clock domain crossing
Digital clock manager
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