Transport through single dopants in gate-all-around silicon nanowire MOSFETs (SNWFETs)
Bai HongYoonhyuk JungS. W. HwangKeun Hwi ChoKim Hwang YeoYun Young YeohS. D. SukMei LiDong-Won KimD. ParkKeun OhW.-S. Lee
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Abstract:
Temperature (T) dependent transport measurements of cylindrical shaped gate-all-around silicon nanowire MOSFETs (SNWFETs) were performed. Single electron tunneling behaviors were observed at 4.2 K and one of the devices exhibited anomalously strong current peak which survived even at room temperature. The observed peak was interpreted as an evidence of transport through single impurities in the channel.Keywords:
Silicon nanowires
A silicon-on-insulator-(SoI)-like bulk silicon (SL-BS) MOSFET structure is proposed and compared against an fully depleted SoI MOSFET using 2-D numerical simulations. The SL-BS MOSFET contains a p/n-/p structure, with n- is made of 4 H-SiC. This n- layer is fully depleted through the built-in potential of two p-n junctions. Simulations indicated that the proposed structure is better than SoI in short channel effects simulation except the threshold rolloff, and equivalent with SoI in single-event upset properties. The SL-BS MOSFET exhibits no significant self-heating effect. Overall, the simulation results indicated the proposed structure is suitable for replacing SoI technology for applications in environments with high-dose radiation.
Short-channel effect
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This chapter describes a high-temperature-operation-tolerant (HTOT) metal oxide semiconductor silicon-on-insulator (SOI MOSFET) and shows the preliminary results of a simulation of its characteristics. This demonstrated that HTOT SOI MOSFET operates safely at 700 K with no thermal instability because of its expanded effective bandgap. It showed that its threshold voltage is higher than that of the conventional SOI MOSFET because its local thin Si regions offer an expanded effective band gap. The HTOT SOI MOSFET with 1 nm thick local-thin Si regions is shown to be almost insensitive to temperature for T < 700 K (427 °C). This confirms that HTOT SOI MOSFET is a promising device for future high-temperature applications.
Power MOSFET
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For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.
Short-channel effect
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The device characteristics of a quasi-SOI power MOSFET were investigated to obtain its optimum device structure. The oxide at the original bottom surface of the bulk power MOSFET of the quasi-SOI power MOSFET formed by reversed silicon wafer direct bonding acts as the buried oxide of the conventional SOI power MOSFET. The short channel effect of the quasi-SOI power MOSFET was larger than that in the conventional SOI power MOSFET. It was suppressed by increasing the width of the oxide in the body region, and the parasitic bipolar effect was suppressed by decreasing it. We also propose a new device structure which can suppress the short channel effect and parasitic bipolar effect of a quasi-SOI power MOSFET based on the results of these experiments.
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Capacitive coupling
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A new method for measuring the output (I/sub D/-V/sub D/) characteristics of SOI MOSFET's without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 μm bulk and SOI MOSFET's with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated.
Power MOSFET
Transient (computer programming)
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A physical model of partially depleted SOI MOSFET was proposed.The SOI MOSFET can be regarded as the combination of bulk silicon MOSFET and bipolar transistor.The model is obtained through detailed analysis of operation mechanism of SOI devices.The model parameters are extracted.The data obtained from this analytical model are compared with device simulation.Excellent agreement is obtained.
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Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.
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New two-dimensional analytical models for the potential distribution and the subthreshold factor in SOI MOSFET are developed and extensive study of 0.1 ?m SOI MOSFET design is performed. It is shown that the ultra-thin SOI films and high doping concentrations are necessary to obtain high subthreshold slopes in SOI MOSFETs.
Subthreshold conduction
Subthreshold slope
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In this work, a two dimensional (2D) Rectangular recessed channel (RRC) metal oxide field effect transistor using silicon on insulator (SOI) is designed and simulated using ATLAS 2D device simulator. The effect of RRC-SOI on analog (DC) and radio frequency (RF) parameter is investigated and the significance of this device over RRC MOSFET about short channel effect (SCE) is analyzed.
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