Hardware accelerated multichannel receiver
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Software-based radios implemented on general-purpose processors are cheaper, easier, and faster to develop, maintain, and upgrade than hardware-based equivalents. Unfortunately, today's general-purpose processors are not fast enough to process certain waveforms. The current alternative is to use application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) for all the signal processing. These operate at very high speeds but are dramatically more expensive and require lengthy development cycles. A single, often small, block is responsible for the bulk of signal processing in a large class of radios. It is therefore very wasteful to implement all the signal processing in a high-speed device such as an ASIC or FPGA. In this paper, we present a software-centric architecture that offloads only the most computationally expensive tasks to an FPGA. The resultant system combines the advantages of both platforms, while minimizing the disadvantages of each. An open-source software radio platform is combined with a consumer off-the-shelf (COTS) FPGA development board to create a hardware-accelerated multichannel receiver. The FPGA is efficiently utilized by partitioning the device into multiple accelerator regions and taking advantage of runtime partial reconfiguration to reconfigure each region as needed during operation. Comparisons between a software-only receiver and a hardware-accelerated implementation are performed.Keywords:
Application-specific integrated circuit
Control reconfiguration
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Reconfigurable Computing
Partial dynamic reconfigurable (PDR) systems designed with state-of-the-art tool chains, like the Early Access Partial Reconfiguration (EAPR) Flow from Xilinx, don't exploit the flexibility provided by dynamic an partial reconfiguration features a state of the art FPGA chip offers. For example the utilized chip area and the position for a dynamic area on the chip is traditionally fixed during design-time. Thereby the shape and the size of the area is given by the largest module. If a smaller module is placed on the region of a bigger one, chip area stays unused. These mentioned restrictions are only some examples for the current support of development and run-time tools for reconfigurable hardware architectures. A new approach is shown for exploiting the capability of reconfigurable hardware architectures more efficient than other solutions introduced before. This is achieved through a novel concept of using micro blocks for the communication infrastructure as well as for the functional elements on the FPGA. The granularity of the micro blocks for building up more complex structures on the FPGA is discussed in this paper.
Control reconfiguration
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This paper gives an overview of in-flight reconfigurable FPGA-based space systems. Firstly, an introduction is presented regarding issues of FPGAs in space systems such as: types of FPGAs being used, the increasing use of FPGAs to the detriment of non-programmable devices, the project phases in which FPGAs are being used, the types of FPGA reconfiguration being considered, and the applications of in-flight reconfiguration of FPGAs. Secondly, this paper introduces the architecture of in-flight reconfigurable FPGA-based space systems platforms and a prospective self-repairing multi-FPGA system that uses in-flight reconfiguration for failure recovery. Thirdly, the essentials of the reconfigurable systems of two European space missions to be launched in the near future are explained here, focusing on their in-flight reconfiguration capability.
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This work presents a dynamically reconfigurable platform called EXPRESS-1, which uses the commercially available embedded processor FPGA. The system makes the most of a fully reconfigurable logic part to explore the area of fine-grained reconfigurable computing. A dynamic reconfiguration mechanism is implemented utilizing a real-time operating system, so device reconfiguration in response to application demand works without suspending other services. EXPRESS-1 features a transparent execution mechanism. Whether a function is executed by the hardware or software, the mechanism frees users from awareness of its execution manner. Furthermore, there is no need to explicitly specify reconfiguration commands into a program because the system determines if reconfiguration is needed based on current conditions. The development of EXPRESS-1 and the runtime reconfiguration mechanism of the fully reconfigurable logic are described. System capabilities are also reported through fundamental evaluations with some practical applications such as JavaVM, encryption processing, and image processing.
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Reconfigurable computing systems show the advantage of high flexibility and high-performance or low-power relative to traditional computing systems. Reconfiguration can change user logic statically or dynamically. The reconfiguration is a key feature in the reconfigurable computing system, however, the reconfiguration techniques are not considered enough. One of the reconfiguration techniques must be chosen for usage target characteristics of reconfiguration. This article shows the cost of typical reconfiguration techniques which can be applied to not only field-programmable gate arrays (FPGAs) but also coarse-grained reconfigurable arrays (CGRAs). We call these microarchitectures, field-programmable logic (FPL). We focus on three device classes; traditional configurable FPL (ex. FPGA), a partially reconfigurable FPL and a multi-context FPL. We investigate how the size and frequency of reconfiguration can be taken care of and how much speed-up is theoretically expected from a perspective of reconfiguration cost. In addition, the investigation introduces temporal and spatial configuration cache techniques.
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Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.
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Control reconfiguration
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Reconfigurability of Field Programmable Gate Array (FPGA) makes it one of the most promising approaches in the implementation of reconfigurable systems. Partitioning the reconfigurable system to many Reconfigurable Modules (RMs) and allocating them into Reconfigurable Regions (RRs) on the FPGA is a challenging task for the system designer. Partitioning choices impact the area efficiency and the time of reconfiguration of the reconfigurable systems. In this paper, different partitioning techniques are studied and evaluated according to their impact on reconfiguration time and the area utilization. Also, a new proposed Dynamic Partial Reconfiguration (DPR) tool flow is presented that automates and optimizes the partitioning procedure based on a graph clustering algorithm, modifies the design's HDL files as per the partitioning results, and implements a routing switch to dynamically change routing between Reconfigurable Regions (RRs) during reconfiguration.
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Recently,with the rapid development of micro-electronic computer technology,especially with the appearance of large scale Field Programmable Gate Array(FPGA),real-time circuit reconfiguration is becoming a research focus among the international academy.Reconfiguration system based on FPGA is self-adaptive and self-repairing,and plays an important role in space applications.The taxonomy for FPGA reconfiguration and dynamic reconfiguration technology is introduced in this paper,Based on FPGA devices,a sort of reconfigurable computing system is proposed that is combining micro-processor(ARM)with multi-FPGA,adopting a new kind of method which is called Boundary-Scan chain to implement partial dynamic reconfiguration.The advantages are more universal and suit for modularized design and so on by configuring multi-FPGA.
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