Large-scale Ge-on-Insulator wafers using low-temperature bonding and Epitaxial Lift-Off (ELO) technique
Eiko MiedaTatsuro MaedaTetsuji YasudaAyumi MaedaYuichi KurashimaHideki TakagiTakuya AokiTaketsugu YamamotoOsamu IchikawaTakenori OsadaM. HataHiroshi AshiharaToyomi WasedaJ. YugamiToshiyuki KikuchiYasuo Kunii
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We have realized patterned Ge-on-Insulator wafers by large-scale layer transfer technology. In conjunction with low-temperature bonding and patterned Epitaxial Lift-Off (ELO) technique, high quality Ge layer transfer was achieved in full-wafer scale.Keywords:
Wafer Bonding
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Wafer-scale integration
Current status and future perspectives for SOI (silicon-on-insulator) using Smart Cut technology will be reviewed. First, industrial growth of SOI production mainly driven by MRJ and low-power LSI applications will be presented, with a focus on the rapid growth of 300mm SOI wafer production and advancement of Si thickness control. Next, versatility of the bonding (Smart Cut) technology will be described, exemplified by the future device candidates, such as strained-Si on insulator, ultrathin FD structures, FinFET, combination of different crystal orientations, and Ge-on-insulator. Thirdly, it will be shown that bonding technology can be extended to realize totally different functions, such as SO (silicon-on-quartz) and combination of Si technology with compound semiconductors, which cannot be realized by conventional bulk Si nor bulk compound semiconductors. Throughout this presentation, it will be shown that wafer bonding technology provides not only solutions for survival of CMOS scaling, but also contributes to diversification of functionality in LSIs, which will meet the needs of the future IT society.
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As the demand for advanced semiconductor packaging technology continues to rise, achieving precise control of the wafer bonding process becomes increasingly critical for optimal performance. This research paper focuses on the development of a fine-pitch hybrid wafer bonding technique specifically designed for heterogeneous integration applications. The objective is to enable high-density interconnections and enhance electrical performance through the bonding of Cu and SiO 2 wafers featuring 15μm spaced Cu pads. The experimental section provides a comprehensive account of the study, covering various aspects such as layout design, preparation, and the bonding process. This includes the fabrication of Cu pads and SiO 2 passivation layers, chemical mechanical polishing (CMP), and alignment bonding. Furthermore, the research also investigates Cu-Cu die-to-die bonding utilizing a (100)-oriented single-crystal Cu top die paired with a Si substrate. Microstructure analysis demonstrates a well-fused bonding interface characterized by a highly preferred (100)-oriented Cu film. The insights obtained from this study contribute to the advancement of wafer-level hybrid bonding techniques for three-dimensional integration technology. This research serves as a valuable contribution to the ongoing development and refinement of advanced semiconductor packaging methods.
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An RF MEMS capacitive membrane switch with interconnects and bonding surfaces for wafer-scale packaging is demonstrated for 50-90 GHz with un-bonded cap wafers
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An overview is given on the use of wafer bonding for formation of Silicon-On-Insulator (SOI) materials for high performance applications. Recent developments in wafer bonding and available techniques for formation of thin semiconductor films is presented. Furthermore, a review is given on results in use of wafer bonding for formation of advanced SOI-materials. Finally, a more detailed discussion is given on the use of wafer bonding for manufacture of SOI-materials intended for high-frequency applications and SOI-materials with films of electrically insulating but highly thermally conductive materials as buried insulators.
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This paper describes techniques for the miniaturized, low-cost wafer level chip-scale packaging of MEMS based system in packages (SiPs). The approaches comprise permanent bonding of cap structures using adhesives or solder onto a passive or active silicon wafer which is populated with MEMS components or which is itself a MEMS wafer. The paper addresses different options for manufacturing of lid or cap structures and their subsequent bonding to the partner wafer. Different technologies like bonding of full area cap wafers as well as partial capping approaches based on reconfigured cap structures on a help wafer or cap structures created on a compound wafer are presented. Examples like the selective capping process for RF-MEMS switches are discussed in detail. All processes were performed at 200 mm wafer scale.
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This study presents groundbreaking outcomes of 400nm pitch wafer-to-wafer (W2W) hybrid bonding connections with a Cu/SiCN bonding interface. A new test vehicle is introduced and meticulously designed for the relevant process development and studies. To ensure a precise surface topography control after CMP, a hexagonal pad grid is adopted, with dummy pads strategically placed in the unused layout areas. The design contains a large range of pad pitches from 1000nm to 400nm, accommodating both equal and unequal pad size configurations. Improved underlayer topography control emerges as a significant factor in achieving void-free bonding. Furthermore, the measured electrical data demonstrates close alignment with simulated models, encompassing resistance and capacitance. The impact of local pad-to-pad overlay error on the electrical properties of hybrid bond pads are also explored in this paper. The findings confirm the necessity for a maximum vector overlay tolerance of 100nm for 400nm pitch connections.
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The smart-cut process is an alternative route to the former silicon on insulator (SOI) material technologies such as SIMOX (separation by implanted oxygen) and BESOI (bonded and etch back SOI). It is based on proton implantation and wafer bonding associated with a temperature treatment which induces a in-depth splitting of the implanted wafer. In this paper, basic mechanisms of bonding and the splitting are discussed. Finally the characteristics of the final structure are presented.
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