Line-frequency doubling of directed self-assembly patterns for single-digit bit pattern media lithography
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Directed self-assembly is emerging as a promising technology to define sub-20nm features. However, a straightforward path to scale block copolymer lithography to single-digit fabrication remains challenging given the diverse material properties found in the wide spectrum of self-assembling materials. A vast amount of block copolymer research for industrial applications has been dedicated to polystyrene-b-methyl methacrylate (PS-b-PMMA), a model system that displays multiple properties making it ideal for lithography, but that is limited by a weak interaction parameter that prevents it from scaling to single-digit lithography. Other block copolymer materials have shown scalability to much smaller dimensions, but at the expense of other material properties that could delay their insertion into industrial lithographic processes. We report on a line doubling process applied to block copolymer patterns to double the frequency of PS-b-PMMA line/space features, demonstrating the potential of this technique to reach single-digit lithography. We demonstrate a line-doubling process that starts with directed self-assembly of PS-b-PMMA to define line/space features. This pattern is transferred into an underlying sacrificial hard-mask layer followed by a growth of self-aligned spacers which subsequently serve as hard-masks for transferring the 2x frequency doubled pattern to the underlying substrate. We applied this process to two different block copolymer materials to demonstrate line-space patterns with a half pitch of 11nm and 7nm underscoring the potential to reach single-digit critical dimensions. A subsequent patterning step with perpendicular lines can be used to cut the fine line patterns into a 2-D array of islands suitable for bit patterned media. Several integration challenges such as line width control and line roughness are addressed.Keywords:
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A combination of simulation, resist modification and process optimization were used to develop production worthy dry 193nm lithography processes, suitable for the metal trench layers of 65nm node logic devices. The important performance characteristics of a back-end metal trench layer are through-pitch proximity bias, lithographic latitude and ultimate resolution. Simulation results suggested that a moderate annular illumination setting balances proximity bias against resolution at the forbidden pitch, yielding a good overall through-pitch common process window. Resist material optimization through resin, PAG (photo-acid generator) and base quencher modification improves proximity bias and results in excellent lithographic performances of good LER (line edge roughness), low MEF (Mask Error Factor) and wider process latitude. To investigate extendibility to 45nm node applications, the immersion compatibility of the optimized resist with several top coats are reported.
Immersion lithography
Process window
Critical dimension
Photoresist
Extreme Ultraviolet Lithography
Shallow trench isolation
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We have evaluated 0.33k1 ArF lithography using 0.63NA scanner to develop 100 nm DRAM. ArF resist problems were resist pattern shrinkage during CD SEM measurement, resist pattern collapse during wet development and poor etch resistance. Off-Site Measurement (OSM) method has been developed for decreasing pattern shrinkage. With OSM method, 8nm of CD shrinkage was down to 2nm for 100nm L/S patterns. We have found a proper BARC material that prevents resist patterns falling down. Lack of etch resistance was compensated by hard mask. With W/SiN hard mask, acrylate- type resist patterns were transferred well into W/poly-Si gate patterns. We have simulated process window of critical DRAM cell patterns (isolation, gate, bit line contact, storage node) in the simple off-axis illumination (OAI) and optical proximity correction (OPC) conditions based on single exposure. Simulation results were verified by lithography tests and it turned out that 0.33k1 process was possible with exposure latitude of above 10% and focus latitude of more than 0.4 micrometers . 0.33k1 ArF lithography was successfully implemented into 100 nm DRAM with CD uniformity of 10nm (3 (sigma) ) and overlay accuracy of 30 nm (mean +3 (sigma) ). We have also evaluated double exposure technique using dipole illumination targeting 90 nm in order to see the possibility of 0.29k1 process. 0.29k1 process was also likely to be possible, although some specific improvements were recommended for the wider process window. From the simulation and resist patterning results, we believe that 0.85 NA lens will be able to extend ArF lithography into 75 nm by single exposure technology using crosspole illumination (0.33k1 process) and 65 nm by double exposure technology using dipole and crosspole illumination (0.29k1 process).
Dram
Process window
Extreme Ultraviolet Lithography
Dynamic random-access memory
Photoresist
Critical dimension
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Double patterning techniques (DPT) with 193nm immersion lithography are being thought to be one of the most promising candidates for the 22nm node and beyond. Especially, self-aligned spacer double patterning (SADP) has already been established as pitch doubling process and adapted in high volume manufacturing of NAND flash memory device. Moreover, ultra fine resolution can be obtained to repeat the SADP step twice as pitch quadrupling. Simple cost effective SADP scheme which is resist core SADP process has already been demonstrated to obtain not only simple line and space patterning also trench and 2D patterning as well by Tokyo Electron LTD.[1, 2, 3] In this process, a SiO2 spacer film is being directly formed on a tri-layer resist stack. This pattern is then transferred onto an underlying spin-on carbon (SOC) film and the final pattern is resolved on the TEOS film. Roughness and verticalness of resist pattern could affect the quality of SiO2 spacer film deposition and it could determine the CD uniformity of final pattern. Therefore, it's been thought that low line-width roughness (LWR) resist pattern and vertical resist profile make a better CD contribution and uniformity on final pattern. Experimental results on SADP process will be shown and then it'll be discussed that specially designed resist materials which indicates small LWR and vertical profile could have a potential to improve CD uniformity after pitch splitting SADP process.
Photoresist
Immersion lithography
Process window
Critical dimension
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In order to extend the optical lithography into sub-72 nm pitch regime, spacer defined double patterning as a self-aligning process option was investigated. In the sidewall defined spacer process, spacer material was deposited directly on the resist to achieve process simplification and cost effectiveness. For the spacer defined double patterning, core mandrel CD uniformity is proven to be a main contributor to pitch-walking and defined a new lithographic process window. Here, the aerial image log-slope is shown to be a measurable predictor of CD uniformity and sidewall angle of the resist pattern. Through resist screening and illumination optimization, resist core-mandrel of 2.5 nm CD uniformity across a focus range more than 200 nm with ± 3.5 % exposure latitude was developed having sidewall control close to the normal. Finally etch revealed that pitch-walking post pitch split can be suppressed below 2 nm within ± 2.5 % exposure latitude.
Mandrel
Process window
Extreme Ultraviolet Lithography
Immersion lithography
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Resist supplier has successfully demonstrated applying negative tone resist into ArF lithography. It is capable of achieving 50nm dense line and <30nm isolated space pattern by over dose operation in topcoat-free immersion lithography. Additionally, using ArF dry system with double exposure could also realize 65nm gridded contact hole patterns. For specific application, negative PR ArF lithography has better benefit of cost and process control capability than other approaches. In this paper, we have determined process capability of 65nm gridded contact hole by ArF dry double patterning and compared with LELE process in terms of DOF, EL and CDU and cost. By continuously optimizing process parameter, >0.21um DOF and 4.6nm global CDU are achieved on DRAM capacitor process. It revealed strong relation to development parameter setting. Furthermore, specific pattern formation considering optical items, ex: OPE, NRF (non-resolution feature) and interaction between double exposure have also been analyzed and difficulties of generating a specific pattern with negative tone resist double exposure have been figured out.
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When technology node transitions to 14nm and beyond, multi-patterning technique including litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) with optical lithography is required to achieve device scaling until extreme ultraviolet (EUV) comes into full production. Although LELE and SADP are widely used and well-studied for line-space layers, the challenge of contact layers still remains unknown. In addition, process window (PW) and pattern defects are often characterized with lithography printability only before 7nm. However, when the gate length is pushed to the limitation of immersion lithography, hard mask open etch (HMO) also needs to be studied along with lithography printability to further optimize overall patterning process window (PW). In this paper, we first studied several optical proximity correction (OPC) techniques such as source-mask optimization (SMO) and sub-resolution assist features (SRAF) to improve PW. We then characterized the patterning PW on several patterning defects including single-layer bridging, multi-layer bridging, missing contact, unlanded contact, and extra contact by tuning develop CD (DCD) and HMO CD (MCD). SMO such as illumination source and projection lens wavefront has been extensively used to enlarge depth of focus (DoF). Two different XY polarizations sources were optimized via SMO and were verified on silicon based on overlap process window and mask error enhancement factor (MEEF). Both sources have achieved <90nm lithography PW and <3 MEEF for the selected SRAM and logic designs. The effect of SRAF size on patterning PW were studied by obtaining DoF and exposure latitude (EL) post develop and post HMO. DoF was enlarged by 20nm when increasing SRAF size; however, EL was reduced by 6% post develop and by 2% only post HMO, suggesting patterning PW should be studied at post HMO instead of post develop. When characterizing multi-patterning PW, two types of defects need to be considered: type 1) single-layer bridging and missing contact driven by lithography only; type 2) multi-layer bridging, unlanded contact, and extra pattern driven by both lithography and HMO. Type 1 defects were studied by lithography printability from focus-exposure matrix for different targets (dense/semi-iso/iso) and maximum lithography PW was achieved by adjusting DCD. Type 2 defects were studied by adjusting both DCD and MCD (etch bias). Missing contact was improved by 20x and unlanded contact was improve by 5x when DCD was increased by 8%; however, multi-layer bridging was worsen by 10x, which can be improved by decreasing MCD by 8%. As a result, overall patterning PW can only be obtained by combining lithography PW and HMO optimization.
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Self-aligned double patterning (SADP) such as multi-patterning process seems to be the most promising technology for 22nm node devices and beyond. In recent years, in order to further scaling, other multi-patterning processes such as self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) have also been studied. However, process cost and CD controllability are major challenges since multi-patterning technology utilizes spacer processes which-requires a larger number of etching and deposition process steps. And then we began to study the simplified spacer process using resist core and we verified its process performance (Process window, LWR) This paper reports on the results of a comprehensive process evaluation of multi-patterning technology using lithography clusters, etching and deposition tools.
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Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moore's Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.
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Reticle
Extreme Ultraviolet Lithography
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The demands imposed by shrinking design rules for sub 20 nm technology on lithographic resolution are driving many avenues of research and development in an attempt to provide a robust and affordable solution for high volume manufacturing. Currently, pitch splitting techniques, such as self-aligned double and quadruple patterning (SADP or SAQP) and litho-etch litho-etch …(LELE…), are being used to bridge the gap to next generation ;lithographic techniques. Cost of ownership (CoO), process window improvements and defectivity are opportunities and concerns for extensions of these approaches, such as resist sliming on sidewall-image transfer (SIT) processes like SADP or SAQP. A spin-on resist slimming approach is implemented with line and space resist to explore process window improvements. The effects of typical process conditions and incoming variability are studied using a custom design of experiments. The optimized process is then used to evaluate process window gain compared to the process of record.
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Trim
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Extreme ultraviolet (EUV) lithography has overcome significant challenges to become an essential enabler to the logic scaling roadmap. However, it remains limited by stochastically driven defects, such as line breaks and line bridges for aggressive pitches. This is especially relevant for the back end of line, which requires the most aggressive scaling. Stochastic defects reduce device yield and may push device manufacturers to move to EUV multipatterning beyond 36 nm pitch single exposure, which is a costly option. While the lithography and patterning stack can be optimized to provide the largest process window with the lowest number of defects, process margins decrease as smaller pitches are required. Currently, for some lithography stacks, especially spin-on glass based trilayer stacks, the defect-free process window beyond 36 nm pitch is limited by line collapse. Reduction in resist thickness may mitigate pattern collapse, but it may also increase the number of line breaks—trading one killer defect for another. In this paper, we expand on an area selective deposition (ASD) process in situ of an etch chamber to selectively deposit material on the EUV photoresist prior to transferring the pattern downstream. We demonstrate mitigation of resist line notching and breaks while maintaining deposition-free open areas and clear alignment marks. Due to the inherent chemical selectivity of the deposition process as opposed to a purely aspect ratio driven deposition process, thinner resists that, with a normal etch condition would result in line breaks, can now be considered. This drives down flopover defect issues seen with thicker EUV resists and enables several underlayer systems that could otherwise not be considered. Finally, we demonstrate that defectivity levels measured by e-beam inspection post lithography and post pattern transfer and yield are both improved at 30 nm pitch when this ASD process is used.
Extreme Ultraviolet Lithography
Process window
Extreme ultraviolet
Photoresist
Deposition
Notching
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