Widely wavelength tunable hybrid III–V/silicon laser with 45 nm tuning range fabricated using a wafer bonding technique
A. Le LiepvreChristophe JanyA. AccardM. LamponiF. PoingtD. MakéF. LelargeJ-M. FédéliS. MessaoudèneDamien BordelGuang‐Hua Duan
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Abstract:
A hybrid III–V on silicon laser, integrating two intra-cavity ring resonators, is fabricated by using a wafer bonding technique. It achieves a thermal tuning range of 45 nm, with side mode suppression ratio higher than 40 dB.Keywords:
Wafer Bonding
Hybrid silicon laser
Direct bonding
Optical ring resonators
GaInAsP surfaces were investigated by contact angle measurement to estimate their hydrophilicity for completing wafer direct bonding. Wafer direct bonding was successfully achieved between O/sub 2/ plasma activated GaInAsP and garnet crystals.
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A methodology allows fabrication of silicon-photonic devices in standard silicon wafers, eliminating the need for silicon-on-insulator (SOI) wafers. Using this technology, the authors demonstrate low-loss silicon waveguides (2.34 dB/cm), comparable to conventional SOI channel waveguides. The ease and flexibility of this fabrication method simplify integration of electronics and photonics and make it a possible alternative to SOI-based technology for implementation of silicon-photonic devices and systems.
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Integrated transmitters incorporating lasers and modulators on silicon are of primary importance for all communication applications, and at the same time are the most challenging to manufacture due to the need of hybrid III-V integration. In order to introduce III-V materials in low cost silicon platform manufacturing, direct bonding approach could present a great interest due to the growth limitation of III-V hetero-epitaxial layers directly onto silicon. Furthermore, by using a 100 nm silicon dioxide layer between the silicon wave guide and the III-V active stack, direct bonding allows the optical coupling necessary to build active optical device. Nevertheless, the potential low cost model of silicon photonic is based only on the hypothesis that we are able to work on the full surface of the 200/300 mm SOI photonic wafer. III-V wafer direct bonding is not suitable to fulfill this requirement for two main reasons. First, the maximum diameter available for III-V wafers is limited to 150 mm up to now. Secondly, the III-V material is necessary only on the emitter and receiver areas which represent only a very little part of the device area. Therefore, the most part of the reported full III-V wafer is lost by the layer patterning on required areas. To overcome this limitation in term of wafer diameter and to limit the loss of a very expensive starting material we have developed at LETI a collective die direct bonding process. The idea is to bond collectively III-V chips only where there are necessary and on the full photonic SOI surface. The die size is selected to be slightly higher than the targeted area in order to be compatible with a wafer notch alignment and avoid any accurate alignment with alignment marks. The requirements for direct bonding are exactly the same than for wafer bonding, but die direct bonding is obviously more difficult due to the dicing step which generates a high level particle contamination. All the process steps have to be adapted to be compatible with die handling and the die cleaning before bonding have to be strongly optimized to remove this high particle contamination. We have then developed specific silicon die holder in order to clean the die surfaces collectively in classical microelectronics high performance cleaning tools. A test vehicle containing few hundred 3*3 mm² dice will be used to evaluate the collective die direct bonding process. Because III-V materials are not as mature as silicon, the bonding process will be firstly evaluated with silicon dies. After optimization, Indium phosphide dice will be used to validate the global process. Bonding interfaces of dice are finely characterized by Scanning Acoustic Microscopy and SAM images will be processed in order to quantify the bonding yield and the die positioning accuracy. Figure 1
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Silicon photonic is the theory and application of photonic systems that utilize silicon as an optical medium. The fabrication compatibility with current CMOS processes offer vast development and future improvement of optical devices. By using silicon micro-ring resonator, the requirement of high speed on-chip interconnections can be achieved. This paper gives an overview of the recent research on the potential of silicon photonics based on micro-ring resonator
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We demonstrate flexible silicon photonic devices, including ring resonators and Mach-Zehnder interferometers, by transferring from SOI wafer to PDMS. Optical characteristics of these devices could be tuned by deforming the flexible substrate.
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Wafer bonding technology was investigated to integrate active photonic devices on a silicon on insulator (SOI) wafer for very compact photonic-integrated circuits. A single-quantum-well (SQW) GaInAsP/InP membrane structure bonded onto an SOI wafer was successfully obtained by a direct bonding method with a thermal annealing at 300-450/spl deg/C under H/sub 2/ atmosphere. The PL intensity of the SQW membrane structure did not degrade after this direct bonding process and its spectral shape did not change. This wafer bonding technique can be applied to realize a direct optical coupling through SOI passive waveguides from membrane active region.
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Wafer bonding technology was investigated to integrate active photonic devices on a silicon-on-insulator (SOI) substrate for highly compact photonic integrated circuits. A single-quantum-well (SQW) GaInAsP/InP membrane structure bonded onto an SOI substrate was successfully obtained by a direct bonding with thermal annealing at 300–450 °C in H 2 atmosphere. The photoluminescence intensity of the SQW membrane structure did not degrade after this direct bonding and its spectral shape did not change. This wafer bonding technique can be applied to the realization of direct optical coupling using SOI passive waveguides from a membrane's active region.
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We demonstrate chip to wafer assembly based on aligned Cu-Cu direct bonding. A collective die surface preparation for direct bonding has implemented to develop dies direct bonding, defect free. An accurate pick and place equipment was adapted to ensure a particle free environment. After a damascene-like surface preparation, chips were bonded with less than 1μm misalignment. 400°C bonded daisy chains on die to wafer structure are perfectly ohmic. Concurrently, to overcome speed limitation of pick and place technique, a self-assembly technique chip is developed. This technique is based on capillary effect for self alignment and direct bonding for assembly. A less than 1 μm alignment accuracy and a 90 per cent self assembly process yield are obtained.
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Successful direct wafer bonding between InP and silicon-on-insulator (SOI) wafers has been demonstrated by adopting a 20-nm-thick Al2O3 as the intermediate layer. A detailed investigation on the property of the bonding interface is carried out. Water contact angle test reveals an improved hydrophilicity for both the InP and the Al2O3/SOI wafers after oxygen plasma surface activation. X-ray photoelectron spectroscopy is employed to characterize the bonding interface before and after the wafer bonding process. It is found that oxides are formed on the bonding interface during bonding, which helps ensure high quality hydrophilic bonding.
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