Automatic generation of software/hardware co-emulation interface for transaction-level communication
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This paper presents a methodology for generating interface of a co-emulation system where processor and emulator execute testbench and design unit, respectively while interacting with each other. To reduce the communication time between the processor and emulator, data transfers are performed in transaction level instead of signal level. To do this, transactor should be located near the DUT mapped on the hardware emulator. Consequently transactor is described in a synthesizable way. Moreover, the transactor design depends on both emulator system protocol and DUT protocol. Therefore, transactor description would not only be time-consuming but also error-prone task. Based on the layered architecture, we propose an automated procedure for generating co-emulation interface from platform-independent transactor. We have also discussed about the practical issues on multiple channel and clock skew problem.Keywords:
Interface (matter)
Hardware emulation
Device under test
Test and verification are essential parts during a product's development cycle. Simulation and emulation are well known techniques to test and verify the functionality of a design-under-test (DUT) before its tape-out. However, there are additional issues like peak power consumption and supply voltage drops, which can compromise a hardware's functionality. These issues are only partly covered by nowadays functional hardware emulation test and verification approaches. This paper presents a comprehensive emulation methodology. It combines functional hardware emulation with model-based performance, power, and supply voltage analysis techniques. The DUT, which has to be available in a hardware description language, is integrated into a FPGA along with designated analysis units. These analysis units implement models of the DUT's performance, power consumption, and supply voltage behavior. The presented emulation methodology allows a designer to test designs in such a way that the cycle accurate results are taken online, in real-time, and verify both functional and performance behavior, as well as power consumption and supply voltage levels. The proposed comprehensive emulation methodology is used, as an example of application, to verify the design of a LEON3 multi-core processor system as well as a RF-powered contacatless smart card. The depicted results demonstrate that this emulation approach is suitable to detect functional misbehavior caused by power and supply voltage hazards and how they influence the performance of the system.
Hardware emulation
Device under test
Automatic test equipment
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Hardware emulation
Instrumentation
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Hardware emulation
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Hardware emulation
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The emulation and functional validation are essential to assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection networks architecture. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy, and decrease usage of the resource of field programmable gate array.
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Fault injection
Integrated modular avionics
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This article aims at computer entity emulation requirement to fit for emulation design and experiment in many actual engineering fields. Expatiate on the design idea and method according to the principle from computer graphics and use senior program design language in the computer emulation system. It will introduce the function and composition of the program module about geometry information,function information and entity model,feature model in this system. It will also show out the ways to set up this emulation system and the processing drafts.
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Functional validation of complex designs by means of hardware prototyping (emulation) is a major tool used by industry to improve the validation quality at the different chip design program phases. However, fitting a design into emulation is not a simple task. Lots of elements collide in orthogonal domains, while trying to get emulation going. This paper goes through selected topics in ramping up a large emulation program, emphasizing items that worth looking into, in order to render the emulation program feasible and effective. This paper does not involve specific project numbers and statistics. However, it is based on the experience from complex design emulation programs.
Hardware emulation
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