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    The future of CMOS scaling - parasitics engineering and device footprint scaling
    H.‐S. Philip WongLan WeiJie Deng
    We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch, which provides performance improvements at both the device and circuit level.
    Parasitic extraction
    Footprint
    Parasitic capacitance
    Citations (3)
    CMOS Technologies for VLSI Circuits
    Symposium on VLSI Technology (1981)
    S. KohyamaTai Satô
    Integrated injection logic
    Citations (4)
    A tunable CMOS read-out integrated circuit for carbon nanotube-based bio-sensors
    IEEE International Instrumentation and Measurement Technology Conference (2011)
    George Yu-Heng LeeSaiyu RenSang Nyon KimRajesh R. Naik
    A robust and tunable read-out integrated circuit architecture is presented for carbon nanotube-based bio-sensor with nano-amperes current measurement at 1ms to 16 minutes intervals. The circuit contains an on-chip 8-bit analog-to-digital convertor and a trans-impedance amplifier with tunable control parameters to accommodate not easily controlled single-walled nanotube sensor fabrication with a wide distribution of resistance ranges. For one of the prepared carbon nanotube devices, the current estimation accuracy is within 0.38 nA for a carbon nanotube sensor with expected effective resistance range between 5-30 MΩ This corresponds to current measurements between 5-45 nA. This CMOS instrumentation core has an approximate area of 639 μm 2 and consumes 33 mW at 5 MHz sampling rate.
    Citations (4)
    Comparison of bulk silicon and SOS for VLSI CMOS
    International Electron Devices Meeting (1980)
    A. Aitken
    Results will be discussed which indicate that both 2um bulk silicon and SOS/CMOS technologies have potential for nanosecond gate delays. The potential reduction in performance of SOS devices due to the floating substrate will be discussed. The analogue capability of present generation CMOS will be described as it can be very efficiently interfaced on-chip with high speed digital circuitry for combined analogue-digital applications.
    Silicon chip
    Citations (6)
    Simulation-based comparison of CNT-FETs and G-FETs from a circuit designer's perspective
    2022 IEEE International Symposium on Circuits and Systems (ISCAS) (2015)
    Manuel Porcel de SotoJosé M. de la Rosa
    This paper compares the performance achieved by carbon-based field-effect transistors made up of either carbon nanotubes or graphene, based on the SPICE models reported for the electrical simulation of these devices. The results achieved by these models are compared with silicon-based conventional CMOS devices, in terms of their main electrical (I DS -vs-V DS and I DS -vs-V GS ) characteristics as well as their fundamental performance metrics, including the intrinsic voltage gain, A v , transconductance efficiency, g m /I DS , and transit frequency, f T . These figures of merit are obtained for diverse biasing and sizing conditions, and discussed from a circuit designer's perspective, in order to determine the benefits and drawbacks of the materials and devices under study. As an application, some carbon-based basic analog and digital circuits are designed and compared with their CMOS counterparts, in order to highlight their potential advantages in each case 1 .
    Citations (0)
    Semi-empirical SPICE models for carbon nanotube FET logic
    Chris DwyerMoky CheungDaniel J. Sorin
    To evaluate the potential of carbon nanotube field effect transistors (CNFETs) to replace silicon CMOS technology, we develop a SPICE model of CNFET nanoelectronics. Our model is parameterizable, and it enables composition of models of various aspects of nanoelectronic behavior. Comparing CNFET nanoelectronics against current CMOS technology and future projections for CMOS, we demonstrate that CNFET nanoelectronics can achieve significantly greater performance at a fraction of the switching energy.
    Nanoelectronics
    Spice
    Semiconductor device modeling
    Citations (70)
    A CMOS ASIC for differential read-out of ISFET sensors
    L. RavezziDavid StoppaM. CorraG. SonciniG.‐F. Dalla Betta
    We report on a CMOS ASIC especially taylored for the differential read-out of ISFET sensors, to be used for remote monitoring of water pollution and for biomedical diagnostic and analysis. The circuit design is based on switched-capacitors technique, which allows a high resolution to be achieved. The first chip prototypes have been fabricated in 0.8 /spl mu/m, 5 V CMOS technology, and are currently being tested. Preliminary results from the electrical characterisation of the chip are reported, which validate the design approach.
    ISFET
    Application-specific integrated circuit
    Citations (6)
    Ultra-Low Voltage Analog Design Techniques for Nanoscale CMOS Technologies
    IEEE Conference on Electron Devices and Solid-State Circuits (2006)
    Peter R. KingetShouri ChatterjeeY. Tsividis
    This paper reviews the challenges and opportunities for ultra-low voltage analog integrated circuit design. The continuing scaling of CMOS technology feature sizes forces a proportional reduction of the supply voltage. The ultra-low supply voltages, down to 0.5 V, projected for the nanoscale CMOS technologies requires drastic changes in the basic circuit topologies used in analog integrated circuits. We explore the combined use of the gate and body terminal of the MOS transistor for signal input or bias control. We illustrate several true-low voltage OTA design and biasing techniques in a fully integrated 0.5 V varactor-C active filter implemented in a standard 0.18 μm CMOS technology.
    Biasing
    Mixed-signal integrated circuit
    Citations (25)
    CMOS interface circuits of capacitive biosensors
    Institution of Engineering and Technology eBooks (2021)
    Ebrahim Ghafar‐ZadehSaghi Forouhi
    Chapter Contents: 4.1 Different CMOS interface circuits of capacitive biosensors 4.1.1 Charge-sharing method 4.1.2 Charge-sensitive amplifier-based and SC techniques 4.1.3 CFC using a comparator-based relaxation oscillator 4.1.4 RO-based CFC 4.1.5 VCO-based sensors 4.1.6 Lock-in detection 4.1.7 Triangular voltage analysis 4.1.8 Charge-based capacitance measurement 4.1.9 Comparison of different capacitive sensors 4.2 Some nonidealities of CBCM 4.3 Core-CBCM interface circuits 4.3.1 Core-CBCM capacitive biosensors using discrete components 4.3.2 Current mirror integrated with CBCM structure 4.3.3 Non-differential CVCs 4.3.4 The CVCs based on differential voltage 4.3.5 The single-ended circuits based on differential current 4.3.6 The fully differential circuits based on differential current 4.3.7 Core-CBCM CFC 4.3.8 Core-CBCM capacitance sensor with nanoelectrodes 4.4 Summary
    Differential capacitance
    Citations (0)
    A CMOS integrated circuit for DNA hybridization detection with digital output and temperature control
    Alessandra CaboniDaniela LoiMassimo Barbaro
    A CMOS integrated circuit hosting an array of 80 sensors for DNA hybridization detection was designed. Each biosensor is made up of a FET device whose current is modulated by DNA electric charge. The chip incorporates integrated temperature detection for precise assay control and features programmable signal conditioning, amplification and A/D conversion. Successful pre- and post-layout simulations are provided.
    SIGNAL (programming language)
    Citations (2)