C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices
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Non-Volatile Memory
A metal–ferroelectric–insulator–silicon (MFIS) structure using lead–zirconate–titanate (PZT) as the ferroelectric layer and Ta2O5 as the insulator layer is fabricated. This structure is studied for the potential application of nonvolatile memory devices. The Ta2O5 layer is used as a buffer layer to minimize the out diffusion of silicon atoms during heat treatment processes. High frequency capacitance–voltage measurements show a flat band voltage shift of 13 V under a ±15 V writing pulse. The interface-trap density Dit is measured by the conductance method. The MFIS capacitors are shown to have a fatigue lifetime of 1×1011 cycles and 5×107 cycles for 11.4 and 15 V writing pulses, respectively.
Lead zirconate titanate
Non-Volatile Memory
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The compounds of the Sr 2 Nb 2 O 7 (SNO) family are suitable for use as ferroelectric materials for ferroelectric memory field effect transistors (FETs), because these substances have a low dielectric constant, low coercive field and high heat-resistance. In this study, we succeeded in preparing Sr 2 (Ta,Nb) 2 O 7 (STN) capacitors on polycrystalline silicon (poly-Si). From SIMS profiles, no interdiffusion in the STN metal ferroelectric metal insulator semiconductor (MFMIS) structure was confirmed. C – V and I D – V G hysteresis curves which were dependent on ferroelectric polarization were obtained. These capacitors were applied to floating gate type ferroelectric random access memory (FFRAM) cells. The degradation in ferroelectricity of STN capacitors was not observed during FFRAM cell fabrication process. We succeeded in operating FFRAM cells with a lower voltage than that required for PZT and confirmed the drain current difference of 1 or 2 orders at the 30 s after applying write pulses of ±5 V or ±10 V.
Ferroelectric capacitor
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Abstract Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO2) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO2 film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.
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Aiming for future nonvolatile memory applications the fabrication and electrical characterization of 3-dimensional trench capacitors based on ferroelectric HfO 2 is reported. It will be shown that the ferroelectric properties of Al-doped HfO 2 ultrathin films are preserved when integrated into 3-dimensional geometries. The Al:HfO 2 thin films were deposited by ALD and electrical data were collected on trench capacitor arrays with a trench count up to 100k. Stable ferroelectric switching behavior was observed for all trench arrays fabricated and only minimal remanent polarization loss with increasing 3-dimensional area gain was observed. In addition these arrays were found to withstand 2 *10 9 endurance cycles at saturated hysteresis loops. With these report the 3D capability of ferroelectric HfO 2 is confirmed and for the first time a feasible solution for the vertical integration of ferroelectric 1T/1C as well as 1T memories is presented.
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In this study, ferroelectric properties of atomic layer deposited Hf 0.5 Zr 0.5 O 2 (HZO) thin films have been investigated for the development of future ferroelectric random access memory capacitors. A 10 nm thick HZO sample annealed at 400°C for 60 s in an N 2 atmosphere after TiN top electrode deposition showed large switching polarization (~45 μC/cm 2 ) and low ferroelectric saturation voltage (~1.5 V) from pulse write/read measurement. Furthermore, fatigue measurements were performed and no significant degradation was observed until 108 switching cycles at 2 V.
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It is recognized that the conventional model for metal-ferroelectric-insulator-silicon (MFIS) capacitor is always not consistent with the experimental observation very well due to negligence of the history-dependent electric field effect. In this letter, combining the switching physics of ferroelectric with silicon physics, an improved model is proposed to investigate the capacitance-voltage (C-V) characteristic and memory window. For two MFIS capacitors with SrBi2Ta2O9 and Bi3.25La0.75Ti3O12 ferroelectric layers, C-V characteristic and memory window were evaluated, and the results are more consistent with the previous experiments than that of the Lue model. The improved model could be extendedly applied to MFIS structure devices.
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Ferroelectric RAM
Bismuth
Ferroelectric capacitor
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A novel high stability electrode technology with TaSiN as a key ingredient is proposed. Combining it with the reduced pressure annealing for low temperature formation of the SBT film, fabrication of the stacked SBT capacitor on poly Si plug was demonstrated for the first time.
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Metal-ferroelectric-insulator-semiconductor capacitors with Pb(Zr0.53,Ti0.47)O3 (PZT) ferroelectric layer and dysprosium oxide (Dy2O3) insulator layer were fabricated and characterized. The measured memory window of 0.86V was close to the theoretical value ΔW≈2dfEc≈0.78V at a sweep voltage of 8V. The size of the memory window as a function of PZT film thickness was discussed. The C-V flatband voltage shift (ΔVFB) as function of charge injection was also studied. An energy band diagram of the Al∕PZT∕Dy2O3∕p-Si system was proposed to explain the memory window and flatband voltage shift. The charge injection is mainly due to electrons.
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