Evaluation of Cache-Based Memory Hierarchy for HEVC Video Decoding

The intra-frame and inter-frame prediction techniques for video encoding, although not exclusively, are key factors in the architectural design of many codec specifications. Adding to the intense exploitation of the processing resources, video codecs carry a very significant energy footprint when it comes to the data flow between the main memory and the processing unit. The present work provides an evaluation of the cache and main memory hierarchy taking the perspective of the energy-related resources demanded in order to perform video decoding. This paper considers various encoding configurations, video sequences, and cache memory parameters. Our methodology uses HEVC state-of-the-art codecs as a case study and employs memory architecture and power models to properly evaluate the memory infrastructure efficiency in terms of hit ratios and energy consumption. Beyond the data reuse comparison between HEVC encoder and decoder sides (28% lower hit ratios at the decoder on average), our results demonstrate the poor effectiveness of increasing cache capacity for providing energy and performance expressive improvements, as its resources are increased, in a video decoding scenario: 5%–76% of higher memory energy consumption when the cache capacity is increased, on almost all the cases. In view of this result, the exploration of novel memory organizations seems to be advised towards the optimization of video encoding techniques.