2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

The last decade has seen impressive progress in the development of a new computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for finding the ground state of an Ising model; thus, it can efficiently solve NP-hard combinatorial optimization problems [3]. In addition to quantum annealers based on superconducting circuits [1], annealing processors based on CMOS technology have received increased interest and are being developed on the basis of simulated annealing (SA) [2]. However, these CMOS annealing processors (CMOS-APs) have room for improvement, such as: i) expanding the bit widths of coefficients, and ii) increasing the number of spins handled by the processor. To address these challenges, a CMOS-AP based on the processing-in-memory approach (where CMOS circuits and an SRAM are tightly coupled [4]) has been developed. Its key features are threefold: a spin operator (processing local memory) which provides coefficients with expandable bit width and fast parallel spin updates according to the Gibbs distribution; a low-latency inter-chip interface (I/F) connecting two Ising chips, resulting in an increased number of spins; and a highly integrated spin circuit which directly connects the spin operator with the SRAM cell. Installed in a $2\times30$ k spin system, the CMOS-AP demonstrates the capability for multi-chip operation with energy efficiency $1.75\times10^{5}$ higher than running SA on a CPU.