Numerical Studies and Validation of Experimental Pentacene Transistor Characteristics

This paper present a numerical validation of experimental results of Bottom Gate/Bottom Contact Pentacene transistor using SILVACO ATLAS simulator. We investigated the impact of different gate dielectric thickness on transistor performance and we estimated threshold voltage Vth, current ratio I on /I off and saturation mobility μ values. We found that gate dielectric thickness is proportional to Vth and inversely proportional to μ.