Design of Low Power Multipliers Using Approximate Compressors

Approximate computing is one of the most promising innovative methodologies to achieve low power consumption and high performance. In this paper, two designs of approximate 4:2 compressors have been proposed to reduce the latency and minimize the power consumption. DADDA multiplier has been designed using the proposed compressors, and it has been compared with the existing approximate multipliers. Hybrid multipliers consisting of two types of proposed 4:2 compressors have also been designed and included for comparison. Furthermore, an exact DADDA multiplier is also implemented to enable the calculation of power savings for the proposed multipliers. The multipliers are then employed in discrete cosine transform (DCT) for image compression, and the error characteristics such as PSNR and NED are analyzed. Simulation results prove that the proposed approximate multipliers have reduced power consumption when compared to the exact multiplier with the minimum error which makes them suitable for image processing applications. All the simulations are carried out using Cadence Virtuoso® design tools.