A Tightly Coupled Network-on-Chip Router Architecture

Network on Chip (NoC) plays an important role in manycore system. Recent researches on NoC focus on the design and optimization on network separately. This paper describes a tightly coupled NoC router architecture. In this architecture, the router and the core are designed as a whole. The router uses on-chip storage to improve the network performance. Several optimizations are introduced to make better use of the on-chip resource and information. This design can save 9.3% chip area in theory. The experiments results show the optimization on the ejection process can reduce latency by up to 75% and energy consumption by 31.5% in heavy traffic load network. And it can also improve latency by about 20% and energy consumption by nearly 25% under different buffer depth. The results also show that this tightly coupled router architecture can achieve better performance in the large scale network.