Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks

In order to provide ASIC implementations of machine learning algorithms with certain degree of reconfigurability, such that applications like edge computing are able to incorporate these designs in contrast of FPGA implementations due to the requirements of lower power, cheaper cost, and improved security, this paper presents the methodologies used to implement a wide range of gated RNN configurations as a single reconfigurable asynchronous ASIC. This design utilizes the Multi-threshold NULL Convention Logic (MTNCL) asynchronous design paradigm. To create the design, the reconfigurable aspects were analyzed, and determinations were made on how to create individual reconfigurable design components and how to share the signal paths as well as the control that could best achieve the overall objective. The resulting implementation is being fabricated in the TSMC 65nm bulk CMOS process. Transistor-level simulations were performed to characterize the minimum and maximum sized configurations.