Digital Multi-Value Logic Gates for Monolithic GaN Power ICs

In this work we propose a first attempt in the fabrication of a family of monolithic GaN-based quaternary multi-value logic gates (MVL), including QNOT, QNOR, and QNAND in a process flow compatible with enhancement mode (E-mode) power HEMT (BV > 650 V). Integration of MVL with GaN power HEMTs increases logic-state density and allows for the design of smart gate drive circuits with reduced switching loss and ringing when compared to circuits using discrete devices. Using TCAD and SPICE device models calibrated against experimental data we demonstrate the functionality of a quaternary inverter with noise margins NML and NMH above 60% and 50% of the logic state voltage range, respectively. Quaternary logic gates show an average reduction of 27% in area utilization when compared to binary logic gates. Additionally, the layout of a quaternary 16-bit DEMUX circuit is projected to occupy 22.5% less area than its binary equivalent. The application of quaternary MVL to digital control circuits for GaN power HEMTs is expected to reduce total circuit area and consume less power than a binary counterpart.