Characterization of Conventional Asynchronous Counters in Digital Systems

Asynchronous circuit technology has a lot of potential when it comes to lower use of power, high performance, electromagnetic compatibility (EMC) properties, improved noise, low emissions and highly modular digital circuits. This paper reveals the uncertainty behavior of a conventional asynchronous counter of modulo-n counter using Altera Max+plusII simulations. A Complex Programmable Logic Device (CPLD) technology of MAX7000 family was used as a target chip which was executing based on the fastest chip automatically. A few characteristics had been studied using the waveform of timing diagram; consequently the behavior for certain mode of counter had been classified. The behavior of the counter can be predicted ahead for design purpose for certain condition without using CAD tools. The simulation results show that the counters mostly exhibit ambiguity count sequence behavior. Only the up-counter and down-counter with conditions of initial=0 (initial<temporary) and initial=maximum number (initial>temporary), respectively, behave properly count sequence. For future works, it is suggested to study and model the uncertainty behavior of an asynchronous counter including hazard detection techniques.