Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

Abstract In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage V T modulation and power management study on the 45 nm 0.374 μm 2 bitcells and on the ESD functionality as compared to bulk technology.