A low-power direct digital frequency synthesizer architecture for wireless communications

A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 /spl mu/m CMOS technology and features 60 dBc spectral purity, 48 Hz frequency resolution, with only 9.5 mW (@30 MHz, 3.3 V) power dissipation.