7 - Implantation VLSI de l'échantillonnage d'un contour à l'aide d'une spécification flot de données conditionné

The paper presents a novel approach to automatically synthesize a VLSI circuit implementing an algorithm specified and verified with a conditionned data flow graph . An edge sampling algorithm, classically used in image processing, is taken to experimen t the approach. It is specified and verified with the conditionned data flow language SIGNAL. This allows to produce easily, using straitforward rules, the digital logic diagram, which will be exploited by an automatic synthesis CAD software to produce a VLSI circuit.