An efficient resolution enhancement technique flow for 65nm logic poly layer

For the manufacturing of 65nm technology devices, many exposure techniques that have been used in previous technology nodes cannot offer enough process window anymore. Alternating Aperture Phase Shift Mask (Alt-PSM) is one of the few remaining technologies that still offer enough resolution to enable 65nm production. While setting up a 65nm Alt-PSM based resolution enhancement technique (RET) flow many of the mask manufacturability challenges need to be considered and addressed. At the same time OPC complexity is one of the main factors for increased data volume and high mask costs. In this work, logic and embedded memory cells are designed, and based on the specific geometries a manufacturable RET flow is developed. Data complexity reduction and lower mask cost are the primary motives in setting up this RET flow.