A new test circuit for the matching characterization of npn bipolar transistors

A new test macro with an active device array is presented for the mismatch characterization of npn bipolar transistors. The macro contains a CMOS circuit which serves for the selection of each bipolar device individually. For each bipolar device terminal a force/sense method is employed to assure the high voltage accuracy requested for bipolar transistors. The characterization of the array with transistors of different geometry gives a database on chip level for the statistical analysis. Matching parameters are given for collector current, current gain, and base-emitter voltage of a 0.5 /spl mu/m smart power technology. The results agree well with in-line measurements using single device pairs and are comparable to reported values in the literature for corresponding technologies.