Development of a large-scale TEG for evaluation and analysis of yield and variation

We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yield and variation for near-minimum DSM (deep sub-micron) design rules. We have successfully measured yield, failure mode and locations both before and after on-chip high-voltage stress. It was also demonstrated that intra-/inter-die variations in various process/device elements could be quickly diagnosed within a week. The new TEG consists of five chips designed using 130-nm CMOS technology with 100-nm physical gate lengths and five copper interconnect layers. The proposed TEG could provide a strategic standard test structure for diagnosis of SoC yield/variation, as well as a technology standard for measuring electrical dimensions and evaluating charge-up damage.