A 5000-gate CMOS EPLD with multiple logic and interconnect arrays

A description is given of a CMOS electrically programmable logic device (EPLD) with over 220000 programmable elements organized into multiple logic array blocks (LABs) that communicate through a separate programmable interconnect array. Redundancy, for the first time ever in programmable logic devices, is implemented in both arrays to improve yield. Devices of different sizes can be easily constructed by varying the number of LABs and/or macrocells within one LAB. A 2t improvement in yield has been observed