Atomically flat interface for noise reduction in SOI-MOSFETs

New process conditions involving temperature below 900°C, and then compatible with SOI wafers and CMOS technologies, were successfully developed in order to realize atomic flat interface in MOSFETs. The implementation of these processes did not only reduce the variability of electrical performances but also brought the low frequency noise level down, making MOSFETs fabricated on atomically flat surfaces superior to non processed MOSFETs in all aspects. The newly developed low-temperature atomic flat process is paving the way to high-performance high-reliability and low-noise MOSFETs for the realization of the next VLSI on SOI technology.